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Nov 13-16 Munich

USB 3.0 Dual Mode Controller IP

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Description

The USB 3.0 Dual Mode controller is a highly configurable core and implements the USB 3.0 Host functionality or USB3 Device functionality selectable via a register or an external pin. The host/device core can be interfaced with third party USB 3.0 PHY’s. The Dual mode controller supports Host functionality using high performance DMA engine based on xHCI specification exposing either an AHB or AXI interface. The host mode core can be configured to support full fledged xHCI implementations for use in standard PCIe-USB bus adaptors/chip sets or be configured with a subset of features for embedded applications requiring limited host functionality. The pravega dual mode controller supports Device functionality which operates in a cut through mode exposing a native packet interface or exposes either an AHB or AXI interface and including a high performance proprietary DMA engine.
The Dual Mode Controller core is carefully partitioned to support standard power management schemes which include extensive clock gating and multiple power wells for aggressive power savings required for mobile and handheld applications. The controller has a very simple application interface which can be easily adapted to standard on-chip-bus interfaces such as AXI, AHB, OCP as well as other standard off-chip interconnects making it easy to be integrated in a wide range of applications.

Features

  • Host functionality is compliant with xHCI Rev1.0
  • Compliant with USB3.0 Specification Rev1.0
  • Compliant with USB Specification Rev 2.0
  • Compliant with USB2 Link Power Management
  • Supports Aggressive Low Power Management
  • Configurable core frequency: 125, 250, 500 Mhz.
  • Configurable PIPE Interface for USB3.0 PHY: 8,16, 32 bit.
  • Configurable USB2 PHY Interface : 8/16 bit UTMI,8-biot ULPI interface
  • Optional DMA engine for device mode functionality.
  • Optional endpoint zero processor block for processing standard requests for device mode functionality
  • Flexible User Application Logic
  • o Can be adapted by any SoC / OCB interface / offchip interconnects – such as AHB, AXI, PCIe
  • o Configurable Datawidth: 32, 64, 128 bit
  • o Optional native packet interface
  • Simple Register Interface for internal Register
  • Access – AHB Slave or GDA PBUS Interface
  • Pin or register bit to select between host/device
  • Benefits

  • Highly modular and configurable design
  • Layered architecture
  • Fully synchronous design
  • Supports both sync and async reset
  • Clearly demarked clock domains
  • Extensive clock gating support
  • Multiple Power Well Support
  • Software control for key features
  • Multiple loop backs for debug
  • Deliverables

  • Configurable RTL Code
  • HDL based test bench and behavioral models
  • Test cases
  • Protocol checkers, bus watchers and performance monitors
  • Configurable synthesis shell
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T2M提供高质量的已验证IP,包括各种模拟/混合信号,RF,数字和SW系统的解决方案。可用于通信,消费类电子和计算机产品的关键组成部分,包括IoT系统,可穿戴设备,蜂窝电话,平板电脑,M2M,RCU,机顶盒,电视机,DVD播放器和PC芯片组。 无论是fab工厂的工艺 /节点的移植还是特定的系统功能,T2M所提供的IP可以进行设计定制化修改以适合客户的具体要求。