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SoC White Box IPs

3DES1 Core IP

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Description

The DES1 core implements DES and triple DES encryption and decryption in compliance with the NIST Data Encryption Standard. It processes 64- bit blocks, with one, two, or three 56-bit keys. Basic core is very small (3,000 gates).

Enhanced versions are available that support various cipher modes (ECB, CBC, OFB, CFB, CTR. The design is fully synchronous and available in both source and netlist form. Test bench includes the NIST DES test vectors. DES1 Core is supplied as portable Verilog (VHDL version available) thus allowing customers to carry out an internal code review to ensure its security.

A DES encryption operation transforms a 64-bit data block into a block of the same size. The encryption key size is 56 bits, with one to three keys used (one in single DES, two is double DES, and three in triple DES. If two keys are desirable in the 3DES EDE mode, the same key values shall be applied to K1 and K3 inputs of the core. The block performs DES encryption as defined by NIST in
FIPS 46-3.

Features

  • Encrypts and decrypts using the DES Block Cipher Algorithm
  • High throughput: up to 3 Gbps at 750 MHz in 90 nm LV technology
  • Small size: from 3K ASIC gates for a triple DES core
  • Satisfies FIPS 46-3 from the US National Institute of Standards and Technology (NIST)
  • Processes 64-bit data blocks
  • Employs one to three keys of 56 bits each
  • Completely self-contained: does not require external memory
  • Available as fully functional and synthesizable
  • Verilog, or as a netlist for popular programmable devices and ASIC libraries
  • Deliverables include test benches
  • Single-DES No License Required (NLR) option DES1-NLR
  • Applications

  • Secure mobile phone communications
  • Secure RFID
  • Secure Smart Cards
  • Secure financial transactions
  • Deliverables

  • HDL Source Licenses
  • Synthesizable Verilog RTL source code
  • Verilog testbench (self-checking)
  • Vectors for testbench
  • Expected results
  • User Documentation
  • Netlist Licenses

  • Post-synthesis EDIF
  • Testbench (self-checking)
  • Vectors for testbench
  • Expected results

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