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SoC White Box IPs

AES Key wrap IP

OverviewFeaturesRequest Datasheet

Description

AKW1 implements the NIST standard AES key wrap and unwrap. Core contains the base AES core AES1 and is available for immediate licensing.

The design is fully synchronous and available in both source and netlist form.

The core is designed for flow-through operation, with 8/16/32/64/128-bit wide input and output interfaces. AKW1 supports both encryption (wrap) and decryption (unwrap) modes.

Features

  • Small size: AKW1 starts from less than 8,000 ASIC gates
  • Completely self-contained: does not require external memory
  • Supports both encryption (wrap) and decryption (unwrap). Encryption-only and decryption only versions available.
  • Includes AES key expansion
  • 128 and 256 bit AES key encryption keys (KEK) supported.
  • Flow-through design
  • Test bench provided
  • Benefits

  • The core is designed with 8/16/32/64/128-bit wide input and output interfaces. AKW1 supports both encryption (wrap) and decryption (unwrap) modes.
  • Applications

  • AES key wrap per NIST key wrap specification and RFC 3394
  • Deliverables

  • HDL Source Licenses
  • Synthesizable Verilog RTL source code
  • Verilog testbench (self-checking)
  • Vectors for testbench
  • Expected results
  • User Documentation
  • Netlist Licenses

  • Post-synthesis EDIF
  • Testbench (self-checking)
  • Vectors for testbench
  • Expected results
  • Tech Specs

  • AES Key wrap

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