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SoC White Box IPs

I2S Controller Core IP

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Description

I2S Controller is a highly configurable core for use in I2S compliant CODECs. It provides a simple glueless interface to industry standard audio devices. This digital audio controller core is compliant to the dominant audio standard protocol I2S. The core is optimally architected for high performance, low latency and small silicon footprint.

The core is provided with the generic processor bus interface on the system side enabling the core to be used in a variety of applications including SoC applications. The core's simple and configurable architecture is independent of implementation tools and, most importantly, target technologies. I2S core is a cost effective, end-to-end solution that allows the licensees to easily migrate to FPGA,Gate array and Standard cell technologies optimally.

I2S core solution leverages years of experience in creating reusable designs for Ethernet, PCI-X, SPI-4 and Hyper Transport technologies to offer lowest risk in terms of compliance and interoperability.

I2S core has been tested for Amba AHB 32-bit wide interface on the system side and DMA channel support for FIFO data transfer has also been provided in this setup.

I2S Controller is a highly configurable core for use in I2S compliant CODECs. It provides a simple glueless interface to industry standard audio devices. This digital audio controller core is compliant to the dominant audio standard protocol I2S. The core is optimally architected for high performance, low latency and small silicon footprint.

The core is provided with the generic processor bus interface on the system side enabling the core to be used in a variety of applications including SoC applications. The core's simple and configurable architecture is independent of implementation tools and, most importantly, target technologies. I2S core is a cost effective, end-to-end solution that allows the licensees to easily migrate to FPGA,Gate array and Standard cell technologies optimally.

I2S core solution leverages years of experience in creating reusable designs for Ethernet, PCI-X, SPI-4 and Hyper Transport technologies to offer lowest risk in terms of compliance and interoperability.

I2S core has been tested for Amba AHB 32-bit wide interface on the system side and DMA channel support for FIFO data transfer has also been provided in this setup.

Features

  • Compliant to I2S Serial Bus protocol
  • Supports full duplex flow control - 1 PCM playback channel and 1 record channel
  • Supports 8/16/18/20/24/32 bit DAC/ADC resolution through software configuration
  • Supports both 256 and 384 sampling frequency (fs) operating mode
  • Support 8/16/32/48/96/192/44.1/88.2/176.4 KHz audio sample frequency
  • Processor Bus 8/16/32-bit wide Interface on system side
  • Supports 1/2/4 samples per 32 bit packing option through Software configuration
  • Fully synchronous design with serial clock and system clock
  • Interrupt Support for FIFO data read/write
  • Programmable FIFO thresholds
  • Loop back mode for testing purposes
  • Benefits

  • Configurable Options
  • Playback and Record FIFO depths
  • Playback and Record FIFO widths
  • Processor bus width – 8/16/32
  • Synchronous and asynchronous reset
  • Deliverables

  • Parameterized RTL Code
  • Automated and parameterized test bench
  • Test cases
  • Synthesis environment/scripts
  • Design document
  • Acceptance Test Bench Specification (ATS)
  • Software specification

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T2M's range of high quality pre-verified, analog/mixed-signal, RF, Digital and SW system solutions, are used as critical building blocks of communications, consumer and computer products including IoT, Wearables, cellular, tablet, M2M, RCU, set-top boxes, TVs, DVD players and PC chipsets. IPs can be modified to meet the customer's specific requirement be it fab/node porting or proprietary features.