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    SDR PHY for 4G/5G and large MIMO system

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    SDR (Software Defined Radio) platforms have the mix of practical deployment scenarios and high performance computing platforms to scale the simulations to RF. The Jupiter HW uses TCI6638K2K System on Chip(SoC) from Texas Instrument. The SoC brings in enormous computing power to develop PHY and Higher Layer Software. There are 8 C66X DSP cores and 4 ARM cores along with several HW accelerator blocks for functions like FFT, FEC (Viterbi and Turbo), Packet Processing and Security Acceleration. More details of the SoC can be found in the SoC data sheet in TI website.
    Jupiter board has 2 industry standard FMC connectors for interfacing various radio transceiver cards. FMC connectors are glued to the SoC using a high-end Xilinx Ultra Scale FPGA. The FPGA adds enormous computation power for taking care of additional HW accelerations that may be required by the application running on the SoC. Based on the choice of radio module the architecture supports up to 8 transmit and 8 receiver antenna ports. The platform can be used for building application with 4x4 MIMO and channel BW exceeding 60 MHz.
    • The DSPs on the SOC is programmed using the Code Composer Studio, IDE from Texas Instruments.
    • The ARM Cortex A15 cores are programmed with the help of GCC compilers
    • FPGA code is developed using Vivado Tools from Xlinx

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