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    GNSS Multi-Constellation Ultra Low Power Digital IP

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    Multi-frequency, multi-constellation GNSS IP for low power, high sensitivity and high accuracy GNSS receivers. This comprehensive future proof Global GNSS IP is extracted from  5th generation production chip, it is all-in view, multi-frequency and multi-constellation GNSS baseband IP core for integration into SoCs from low power IoT to Automotive Precision Navigation. The feature rich, low power. Low gate count baseband provides ultra -fast acquisition and precision tracking performance achieving a very small size of ~1mm2 in 28 nm. It supports processing two RF channels simultaneously providing dual frequency GNSS capability, along with superior immunity features against pulsed and multitone interference. The IP core is highly SW configurable to support any of the legacy, modernized and potential future GNSS signals of all available constellations, concurrently or sequentially based on the need of the application.
    • Supports all signals in L1, L2, L5 and S band frequencies from GPS, GALILEO, GLONASS, BeiDou, QZSS, IRNSS, and SBAS constellations
    • Efficient and generic PRN code handling architecture to support future signal structures
    • Massive and wide bandwidth correlators enable fast acquisition and high precision
    • Multi-tone continuous wave interference mitigation and pulsed interference mitigation to enable receiver to operate in intentional or unintentional interference environment
    • Processes ADC output from one or two RF front- ends
    • Configurable ADC interface:
    o SDR (sampled data on rising edge) o DDR (sampled data on rising and falling) o various sampling frequencies o real or complex samples o 1-bit to 5-bit ADC data processing
    • Enables PPP and RTK positioning
    • Measurement generation on external event or internal 1PPS event
    • Up to 1KHz measurement rate
    • Battery Backed Counter to maintain GNSS Time
    • AMBA compliant AHB or Synchronous Parallel Bus interface to CPU
    • Patented architecture for lowest power and lower logic area

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