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Multi-Standard SerDes PHY IP

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This SerDes PHY IP meets the requirement of broad range of market segments for machine-to-machine communication with lane configurable, high-speed operation and less Jitter on its output data. The PHY has two layers, logical and electrical. The electrical layer (PMA) handles the high-speed serial packet exchange and power management. The logical layer (PCS) handles reset, initialization, encoding & decoding and loop back testing. Technology
  • TSMC 65nm GP (1.0V ± 10% supply)
  • TSMC 55nm LP (1.2V ± 10% supply)
  •  TSMC 28nm HPC (0.9v ± 10% supply)
  •  GF 28nm LP (0.9v ± 10% supply)
  •  Samsung 28nm SLP (0.9v ± 10% supply)
  • Configurable parallel data support for 8-/16-/32 -bits
  • Support for x1 and x4 macro configuration
  •  Auto calibration for process and temperature (USP)
  •  Operating temperature -40oC to 125oC
  •  SRnS support
  •  Programmable internal/external loopback modes between Tx and Rx.
  •  Standby / power down mode
  •  Low silicon surface
  • Enterprise routers
  •  Data storage
  •  Network communication
  •  Switches
  •  Repeaters and Re-timers
  • Configurable parallel data widths of 8 / 16 / 32–bit
  •  Input reference 125MHz to support 2.5/5/10G data rates & 100MHz to support 2.5/5/8/16G data rates.
  •  Tight control over termination resistor (~50 Ohm) with on chip calibration
  •  Tight skew control of 1UI between lanes of the PMA
  •  Multi-tap Tx Finite Impulse Response (FIR) equalizer with multi-level de-emphasis
  •  Continuous time linear equalizer (CTLE) with programmable settings providing up to 12dB gain peaking at Nyquist frequencies
  •  Programmable/automatic calibration of key circuits (pre-emphasis, eye-diagram monitoring / DFE tap calibration / offset calibration)
  •  CDR logic for better data alignment and locking
  •  Support for bifurcation and quadfurcation modes
  •  Multi-tap Rx DFE (decision feedback equalizer)
  •  Programmable internal/external loopback modes between TX and RX
  •  Includes ESD structures
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