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PCIe 5.0 /4.0 /3.0 Controllers

OverviewFeaturesRequest Datasheet

RC digital IP controller only in verilog EP digital controller only in verilog Dual Mode(DM) controllers in Verilog RC UVM+SVVIP EP UVM+SVVIP DM UVM+SVVIP Hardware validation platform for RC only Hardware validation platform for EP only Hardware validation platform for DM only

  • Compliant with PCI Express 5.0 (32
  • (16 GT/s), (16 GT/s), (16 GT/s), (16 GT/s), & backward compatible. Compliant with Pipe s.x
  • Supports both PIPE SERDES and non Serdes architecture
  • EPI RCI DMI Switch configurations support architecture
  • Compliant with ATS Specification
  • Compliant with AMBA INTERFACES Latest versions
  • 5 12b Controller architecture and 64B PIPE interface for very high performance
  • Compliant with SR -Iov Specifications.
  • Supports X 16, X8, X4, X2, I Lanes
  • Highly configurable, robust DMA Highly architecture
  • Flexible user interface & AXI4/Native Interfaces
  • LTR, AER, OBFF, MSI, MSI LTR, AER, OBFF, ERC, and Cross link all features supported
  • Required features can be turned on and off at core generation
  • Phase for an optimized gate controller
  • Simple Clocking architecture
  • 32 Physical and 512 virtual functions supported
  • Optional lnbuilt address translator Configurable
  • FPGA validation @ Gen4 speed and loopback mode
  • @Gen5 speed
  • PCI SIG compliance test
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