This memory controller supports DDR2/3 SDRAM. DDR2/3 memory controller is a high-speed interface used for data read/write between internal engine and outside SDRAM bus, and transfers the internal signal to meet the SDRAM specification. The DDR2/3 memory controller includes several Sub- Arbiters and a MEM_CORE module. The MEM_CORE module includes a Main-Arbiter module and a DDR controller module. Sub-Arbiter supports 4 masters. Sub-Arbiter would be placed in partition or in memory controller. Main- Arbiter supports 16 masters. The memory arbiter will do arbitration one all the masters’ (internal engines) request and send those request to DDR controller. The DDR controller will convert the internal request to DRAM chip protocol for data read/write. The DDR controller also implements the DRAM refresh, DRAM dynamic power down, DRAM Scramble and DRAM Private Usage functions. The DDR IP is compliant with the latest JEDEC standards and is silicon proven
Supports DDR3/DDR2 SDRAM
16 bits width DDR2/DDR3 SDRAM Interface
Memory Clock up to 462MHz, DFI Clock up to 462MHz
Support DDR2 667/800/1066 and DDR3 667/800/1066/1333/1600/1866
Supports IMB Continuous TX, RX Request mode
Supports Dynamic Enter and Exit DDR3/2 Power-Down Modes
Supports DDR3/2 Self-Refresh function
Supports ALi DFI
Supports up to 16 IMB main-masters
Supports dynamic priority adjustment bus arbitration
128 bits IMB data bus @ Memory Clock
Supports 16 MB – 1GB total DRAM size
Supports Out-of-Range interrupt
Programmable refresh cycle
DRAM Controller Build- in BIST Module, which can send the busiest request to access DRAM.
Supports Video Frame Buffer protection function
Supports IP and System BW Detect (internal use).
Supports ALi DFI any width Bubble Read Valid mode
Supports monitor 2 memory space write operation.
Invalid Masters’ Write will issue interrupt to NB. They can be masked
DDR Controller IP functionality is verified in NC-Verilog simulation software using test bench written in