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    DDR4/ LPDDR4/ DDR3L Combo PHY IP

    OverviewFeaturesRequest Datasheet

    This DDR (Double Data Rate) PHY IP supports DRAM type DDR3L/DDR4/ LPDDR4, this PHY provides low latency, and enables up to 3200Mbps (in TSMC 12FFC), 1866Mbps throughput (in TSMC 28HPC+ & UMC 28HPC+). The DDR IP is compliant with the latest JEDEC standards and is silicon proven. The PHY is optimized for high performance, low latency, low area, low power, ease of integration and faster time-to-market.

    The DDR PHY is interface between DDR controller and SDRAM. The DDR controller is used to control DRAM devices as well as to access the data stored on these devices. Provide multiple AXI interface for AXI master and support DFI standard for DDR PHY to support DDR3L/4, LPDDR4 date rate 1600~3200 Mbps, X8/X16, four ranks, Write leveling, Data training, low power mode and standby mode. The DDR (Double Data Rate) PHY is used to control DRAM devices, to access the data stored in these devices, provide SSTL135, POD12 and LVSTL interfaces for DDR3L, DDR4 and LPDDR4.

      DDR4-LPDDR4-DDR3L-Combo-SERDES-Phy  

    Related Links: Design & Reuse | ChipEstimate | Anysilicon

    • Supported DRAM type: DDR3L/DDR4/LPDDR4
    • Maximum controller clock frequency of 800MHz resulting in maximum DRAM data rate of 3200Mbps
    • Interface: SSTL135/POD12/LVSTL
    • Data path width scales in 8-bit increment
    • Four module for flexible configuration: CA/DQ_X16/DQ_X8/ZQ
    • Programmable output impedance(DS)
    • Programmable on-die termination(ODT)
    • Core power:0.8V
    • ESD : 2KV/HBM, 200V/MM, 500V/CDM
    • Support ZQ calibration
    • Support 4 ranks by each CA module
    • Support write-leveling, CBT
    • Support PHY internal VREFDQ auto decision
    • Support in TSMC 12FFC, TSMC 28HPC+, UMC 28HPC+
    • TSMC 12FFC: Maximum controller clock frequency of 800MHz resulting in maximum DRAM data rate of 3200Mbps
    • TSMC 28HPCP: Maximum controller clock frequency of 400MHz resulting in maximum DRAM data rate of 1600Mbps
    • UMC 28HPCP: Maximum controller clock frequency of 400MHz resulting in maximum DRAM data rate of 1866Mbps
    • Per-bit deskew in read and write datapathTSMC 12nm FFC IP9M 2xa1xd3xe2z AL=28k (ULVT/SVT) process
    • Flip-Chip
    Benefits
    • DDR technology is the de facto memory used in almost all applications today, Ranging from high-performance computing to power/area-sensitive mobile applications.
    • Low Power
    • Low Area
    • Low Latency
    • JEDEC, the standards body responsible for memory standards has defined and developed DRAM categories such as DDR: DDR, DDR2/3/4 mobile DDR: LPDDR2/3/4 high bandwidth DRAM: HBM, HBM2/2E/3)
    • matching Controller with DFI 4.0 Interface
    Applications
    • SSD Controller
    • Digital TV
    • Mobile
    • Data centers (networking and storage)
    • Servers
    • High-performance computing
    • Multimedia
    • IOT
    • Surveillance
    Deliverables
    • User Manual
    • Behavior model, and protected RTL codes
    • Protected Post layout netlist and Standard
    • Delay Format (SDF)
    • Synopsys library (LIB)
    • Frame view (LEF)
    • Metal GDS (GDSII)
    • Test patterns and Test Documentation

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