Display Port v1.4 Tx PHY & Controller IP
- Wireless
- Bluetooth/BLE
- BLE
- Bluetooth
- BT Dual Mode v5.2 RF PHY IP in TSMC 22nm
- BT Dual Mode v5.2 RF PHY IP in GF 22fdx
- BT Dual Mode 5.2 HW Linklayer / BaseBand Controller IP
- BT Dual Mode v5.2 Software Stack & Profiles IP
- BT Dual Mode v5.0 Software Stack & Profiles IP
- Bluetooth MESH v1.1 Software IP
- Bluetooth Dual Mode v4.2 RF Transceiver IP
- Bluetooth Dual Mode SoC White Box IP
- LE Audio
- Cellular
- Audio
- Broadcast
- Lighting
- SerDes
- Controller
- DDR
- PCI Express
- USB
- Controllers
- USB 4.0 Device Controller IP
- USB 4.0 Host Controller IP
- USB 4.0 Hub Controller IP
- USB 3.2 Device Controller IP
- USB 3.2 OTG Controller IP
- USB 3.2 Dual Mode Controller IP
- USB 3.1 Device Controller IP
- USB 3.1 Host Controller IP
- USB 3.1 Hub Controller IP
- USB 3.1 Vision Controller IP
- USB 3.1 Gen1 SSIC Controller IP
- USB 3.0 Device Controller IP
- USB 3.0 Host Controller IP
- USB 3.0 Hub Controller IP
- USB 3.0 Dual Mode Controller IP
- USB 3.0 OTG Controller IP
- USB 3.0 Audio Class Device Controller IP
- USB 2.0 Device Controller IP
- USB 2.0 Host (xHCI) Controller IP
- USB 2.0 Audio Class Device Controller IP
- USB 2.0 OTG Controller IP
- USB 1.1 Device Controller IP
- TSMC 16FF+
- TSMC 22ULP
- TSMC 28HPC+
- TSMC 40LP /LL
- UMC 28HPC+/ HPC
- UMC 40LP
- UMC 55SP /EF
- SMIC 14SF+/ SF++
- SMIC 40LL
- SMIC 55LL
- Controllers
- MIPI
- Controllers
- MIPI UFS v3.1 Device Controller IP
- MIPI UFS v3.1 Host Controller IP
- MIPI UFS v2.1 Host Controller IP
- MIPI CSI-3 Device v1.1 Controller IP
- MIPI CSI-3 Host v1.1 Controller IP
- MIPI CSI-2 Tx v2.0 Controller IP
- MIPI CSI-2 Rx v2.0 Controller IP
- MIPI CSI-2 Rx v1.3 Controller IP
- MIPI CSI-2 Tx v1.3 Controller IP
- MIPI CSI-2 Tx v1.1 Controller IP
- MIPI CSI-2 Rx v1.1 Controller IP
- MIPI DSI2 Tx v1.1 Controller IP
- MIPI DSI2 Rx v1.1 Controller IP
- MIPI DSI Tx v1.2 Controller IP
- MIPI DSI Rx v1.2 Controller IP
- MIPI Unipro v1.8 Controller IP
- MIPI Unipro v1.6 Controller IP
- MIPI I3C Master v1.1 Controller IP
- MIPI I3C Slave v1.1 Controller IP
- MIPI SoundWire Master v1.2 Controller IP
- MIPI SoundWire Slave v1.2 Controller IP
- MIPI RFFE Master Controller IP
- MIPI RFFE Slave Controller IP
- TSMC 12FFC
- TSMC 22ULP
- TSMC 28HPC+
- UMC 28HPC+
- UMC 40LP
- UMC 55 SP
- SMIC 55 LL
- Controllers
- HDMI & DP
- TSMC 12FFC
- TSMC 28HPC+
- HDMI v2.1 Tx-Rx Phy & Controller IP
- HDMI v2.1 Tx PHY & Controller IP
- HDMI v2.1 Rx PHY & Controller IP
- HDMI v2.0 Tx PHY & Controller IP
- HDMI v2.0 Rx PHY & Controller IP
- HDMI-DP Combo Rx PHY IP
- Display Port v1.4 Tx PHY & Controller IP
- Display Port v1.4 Rx PHY & Controller IP
- V-by-One / LVDS Tx IP
- V-by-One / LVDS Rx IP
- TSMC 40LP
- TSMC 65LP / 55LP
- TSMC 65GP / 55GP
- TSMC 90G / 85G
- TSMC 130G / 110G
- UMC 28HPC/HPC+
- UMC 40LP
- UMC 65SP / 55SP
- UMC 110AE
- UMC 130HS
- SMIC 40LL
- SMIC 65LL / 55LL
- SMIC 65G / 55G
- GF 22nm
- GF 28SLP
- GF 65LPe / 55LPe
- Samsung 28FDSOI
- ST 28FDSOI
- STMicro CMOS 40
- IDM 180nm /150nm
- Ethernet
- Video & Graphics
- Analog
- Peripherals
- Services
OverviewFeaturesRequest Datasheet
DisplayPort version 1.4 compliant transmitter PHY supports 1.62Gbps (RBR) to 5.4Gbps (HBR2) bit rate Integrated 100-ohm termination resistors with common-mode biasing Integrated equalizer with tunable strength Configurable analog characteristics CDR bandwidth, Equalizer strength, Terminator resistance, BGR voltage, Regulator voltage, Support PLL test and internal analog signal monitor 1.8V/0.9V power supply.

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- eDP version 1.4a / DP version 1.4 compliant transmitter
- Supports HDCP1.4 and HDCP2.2(Optional)
- Supports Forward Error Correction (Optional)
- Consists of configurable (4/2/1) link channels and one AUX channel
- Supports 1.62/2.7/5.4/8.1Gbps (HBR3) bit rate and all recommended link rate (ie 2.16Gbps etc)
- Supports main link operation with 1 or 2 or 4 lanes
- Supports both Default and Enhanced Framing Mode
- Supports SST mode
- Supports video packet and audio packet (8ch max)
- Supports both Normal and Alternate Scrambler Seed Reset
- Supports E-EDID data reading via I2C-over-AUX transaction
- Supports Video test pattern generator (compliant with DP link CTS v1.2)
- Configuration registers programmable via AMBA interface
- Verilog RTL or netlist source code of LINK controller.
- Abstracted timing models for synthesis and STA
- Timing constrains for synthesis and physical layout
- Behavioural Verilog Model, simulation test bench, run control scripts, and test stimuli
- Physical design database
- Integration guidelines
- Reference software sample code
- Smart TV
- Recorders
- Streaming-media players
- Home theater systems