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    T2M › V-by-One Tx IP

    V-by-One Tx IP

    OverviewFeaturesRequest Datasheet

    V-by-One® HS technology targets a high speed data transmission of video signals based on internal connection of equipment. V-by-One® HS Standard defines the specifications to develop a transmitter and receiver .This Supports up to 4Gbps/lane; and Available 8-lane PHY and 16-lane PHY for Tx and Rx.

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    • Wide-range data rate, up to 1Gbps, the associated clock is DDR clock (1/2 of the data rate, up to 500MHz)
    • 16 channels total 128 bits of parallel data, each channel has a bit width of 8 bits
    • DC coupling mode
    • Multi-channel shared offset
    • Built-in transmitter terminal impedance, no need for off-chip components
    • Support AXI stream bus protocol and data transceiver
    • Built-in self-test mechanism, which can independently complete feature and mass production testing
    • Support link training mode
    • Support Flip-chip package form
    • ESD: HBM/MM/CDM/Latch Up 2000V/200V/500V/100mA
    Deliverables
    • Datasheet
    • Integration guideline
    • GDSII or Phantom
    • GDSII Layer map table
    • CDL netlist for LVS
    • LEF Verilog behavior model
    • Liberty timing model DRC/LVS/ERC results
    Applications
    • Smart Phone
    • Tablet
    • PC
    • Car navigation
    • Smart TV
    • Digital Still Camera
    • HD Camera

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