SoC White Box IPs

Schedule a meeting

Charge Pump PLL IP

OverviewFeaturesRequest Datasheet


This Charge Pump PLL is designed in CMOS LP technology, using seven metallization levels. These voltage pulses are converted to current pulses in the Charge Pump. These current pulses charge or discharge the Loop Filter to generate the control voltage for the VCO. The VCO generates a frequency (FVCO) proportional to this control voltage. This frequency is then divided by the Loop Frequency Divider, to generate FBCLK. 1467182555pll_300


  • Input frequency (MHz): 19.2-40MHz
  • VCO frequency: 1500-3000MHz
  • Output frequency: PHI: 23.4375-1500MHz
  • Uses LVT and SVT devices in GO1 and SVT25 devices in GO2
  • Area: 0.1788 mm2 (Target) (X = 208 m, Y =860 m)
  • Maximum power: 15.22 mW
  • Fractional mode supported
  • Seven metal level technology used for design:
  • 4X (thin) metals
  • 0Y (intermediate) metals
  • 2Z (thick) metals
  • Applications

  • Used in frequency synthesis applications
  • Deliverables

  • Detailed Specification and Integration guide
  • LEF abstract
  • GDSII layout and Mapping files
  • LVS compatible netlist
  • Verilog-A Model
Fill the form below, to receive the product datasheet in your inbox