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MIPI CSI2 SMIA Dual Mode Receiver IP

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The CSI-2 Receiver IP is in charge of handling CSI2 & SMIA protocols, as well as depacking input data to pixels. It also selects the correct destination for each data packet (Bayer input of ISP, RGB/YUV input of ISP, Memory). The IP reorders up to 4 x 1.5 Gbps data lanes, separates sensor clock of CSI-2 Core from DPHY byte clock. IP is able to store in memory all CSI2 datatype and to process rawbayer, compressed rawbayer, yuv pixel reconstruction for on the fly ISP processing. It also performs ECC/CRC check & correction. CSI-2 Receiver IP supports Virtual Channel and Datatype selection. It supports continuous and gated clock configurations.
Main HW modules are -
  • 1. CSI2RX Front handles:
  • o DPHY lanes swapping
  • o Sensor clock isolation
  • 2. CSI2RX Protocol module handles:
  • o CSI2 Protocol (including ECC, CRC, Virtual channel & Data types)
  • o Start/End of frame, programmable & truncated frame interruptions
  • 3. SMIARX module handles:
  • o SMIA ISL lines support
  • o Frame generation on pixel output based on programmed frame format description
  • 4. Output Control module handles:
  • o Virtual Channel / Data type de-interleaving
  • o Command of Depacker module
  • 5. Depacker module handles:
  • o Control of multipurpose FIFO
  • o Byte to pixel conversion
  • o ISL specific depacking
Main interfaces are -
  • 1. APB 32 bits slave interface for register accesses
  • 2. CSI2 DPHY interfaces: Three DPHY interfaces up to 4 Data Lanes
  • 3.Pixel outputs: Two exclusive pixel outputs (1 for RAW Bayer data and 1 for RGB & YUV).
  • 4. Packed outputs: Two packed outputs. These outputs will use srdy/drdy protocol to provide 64 bits packed in bytes.
  • 5.ISL output: One ISL output for each depacker. This output will use srdy/drdy protocol to provide 64 bits packed ISL lines.
  • 6. Memory interface: One memory control interface.


  • Compliant with MIPI Alliance Specification for Camera Serial Interface 2 v1.01 and SMIA 1.0 Part 1 v1.0
  • Support of CSI2 interface up to maximum 4*1.5 Gbps
  • 1 to 3 DPHY interfaces up to 4 data lanes each, compliant with MIPI D-PHY PPI
  • Full byte to pixel conversion
  • Automatic start of frame synchronization when enabled
  • Packed outputs: any format packed on 64 bits
  • Pixel outputs -
  • RAW bayer (6, 7, 8, 10, 12, 14 bpp)
  • YUV422 interleaved raster (8, 10 bpp)
  • RGB888
  • Benefits

  • Configurable DPHY Interface number
  • Configurable Data Lane number (independent for each DPHY I/F)
  • Virtual Channel / Data type de-interleaving
  • Protocol error detection
  • SMIA Protocol handling
  • Byte to pixel conversion
  • Deliverables

  • Configurable RTL Code
  • HDL based test bench and behavioral models
  • Test cases
  • Protocol checkers, bus watchers and performance monitors
  • Configurable synthesis shell
  • Documentation
  • Design Guide
  • Verification Guide
  • Synthesis Guide
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