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The PCIe/SATA combo PHY implements the lower (physical) layer protocols (of SATA,PCI Express) providing data transmission and reception over a dual differential pair cable. The TX (transmit) and RX (receive) serial channels operate plesiochronously (NRZ). The macrocell can be used in Host or Device applications.


  • Serial transceiver (PHYsical layer)
  • Serializer and Deserializer
  • Direct support for 6.0 Gbit/s SATA rates and 5.0 Gbit/s PCI Express
  • Backward compatible with 1.5, 3.0 and 2.5 Gbit/s rates
  • 20-bit parallel interface
  • Comma detect to provide word alignment of incoming serial stream
  • SSC modulation
  • Requires DC-balanced encoding scheme
  • Integrated impedance adaptation to transmission line characteristics
  • OOB signaling
  • JTAG test access port allows:
  • Internal loop-back for self-test
  • Random pattern auto-test
  • 65 nm CMOS technology
  • 1.2 V and 2.5 V power supply
  • High-performance PLL
  • Programmable TX buffer pre-emphasis, slew-rate and amplitude.
  • Dedicated TX buffer regulator giving:
  • improved transmit buffer noise immunity
  • improved buffer level stability
  • Integrated BIST allows:
  • Self test of the macrocell in loop back mode at Gigabit rate on production testers
  • Self test of the macrocell at system level, either in internal/external loop back mode or between different chips in transmission mode
  • Applications

  • SATA (i, m)
  • PCI Express
  • Transmission schemes encoding octets as 10-
  • bit code groups to form a DC-balanced stream
  • High performance backplane interconnect
  • Deliverables

  • RF including schematics, database and test bench
  • RTL source code
  • GDS II production licenses
  • Grey Box (Analog/RF GDSII, Digital, FW, SW as source code)
  • White Box (Source Code of complete design data base)
  • SW source code
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