Production Proven, Complex Semiconductor IP Cores

Semiconductor IP Cores


T2M MIPI A-PHY Tx/Rx IP

MIPI A-PHY Tx/Rx IP

Description

The MIPI A-PHY Tx/Rx IP is a high-speed, silicon-proven physical layer solution designed for next-generation automotive camera, display, and sensor connectivity applications. Developed on TSMC's 12nm/22nm process technology, the IP enables reliable long-reach, low-latency data transmission while ensuring seamless interoperability with a wide range of serializer and deserializer (SerDes) devices.
Compliant with the MIPI A-PHY PAL Layer Protocol Version 1.0 (September 2020), the solution supports data rates of 3.2 Gbps and 6.4 Gbps using NRZ modulation. It incorporates 8b/10b encoding, integrated Forward Error Correction (FEC) for robust error protection, and Clock Data Recovery (CDR) technology to deliver highly reliable communication in demanding automotive environments.
The IP supports up to four high-speed A-PHY links with a 100 Mbps time-sharing reverse communication channel, making it ideal for ADAS, surround-view cameras, digital cockpits, infotainment systems, autonomous driving platforms, and other high-bandwidth automotive applications requiring secure, low-latency, and high-performance connectivity.

 

Features

  • Silicon proven in TSMC 22nm process technology
  • Compatible with MAX96717/MAX96712 serializer/deserializer devices
  • Supports MIPI A-PHY PAL Layer Protocol Version 1.0 (September 2020)
  • Supports 3.2 Gbps and 6.4 Gbps forward data rates
  • NRZ modulation with 8b/10b encoding
  • Integrated Forward Error Correction (FEC) for enhanced link reliability
  • Integrated Clock Data Recovery (CDR)
  • Supports up to four high-speed communication links
  • 100 Mbps time-sharing reverse transmission channel
  • Optimized for automotive camera, display, and sensor connectivity
  • Low-latency, long-reach, point-to-point communication
  • Ideal for ADAS, digital cockpit, surround-view, and in-vehicle networking applications

Deliverables

  • Comprehensive Product Documentation
  • GDSII Database with Layer Mapping
  • Verilog Model for Functional Simulation
  • Liberty (.lib/.db) Timing and Characterization Files
  • LEF Abstract Views for Physical Design Integration
  • CDL Netlist for LVS Verification
  • Design Guidelines, Integration Notes, and Support Files