Description
The 112G SerDes IP Core in 6nm FinFET technology enables ultra-high-speed serial connectivity for next-generation SoCs. Supporting both PAM4 signaling up to 112 Gbps per lane and NRZ modes up to 56 Gbps, this SerDes is tailored for long-reach and short-reach links across diverse environments such as data centers, networking switches, and cloud accelerators.
Its advanced DSP equalization, adaptive clock/data recovery, and reflection cancellation deliver robust performance even over lossy channels. With a low-power, compact architecture, this PHY IP is optimized for high port density, ensuring scalability for large-scale integration.
Features
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Speed Flexibility: 1–56 Gbps (NRZ) and 56–112 Gbps (PAM4).
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Channel Robustness: Long-reach support with adaptive EQ, DFE, and FFE.
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Integrated MCU: Self-startup, link adaptation, and autonomous operation.
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Diagnostics & Testability: PRBS generators/checkers, eye monitoring, BER estimation, and loopback modes.
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Process Node: Proven in 6nm FinFET with superior power-performance efficiency.
Applications
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High-bandwidth data center interconnects
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Cloud servers and hyperscale networking
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AI/ML SoCs requiring low-latency serial links
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Chip-to-chip and backplane communication
Benefits
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High Performance: Reliable operation across lossy and reflective channels.
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Low Power, Compact Area: Optimized for multi-lane, high-density designs.
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Scalable Integration: Configurable for various reach and rate requirements.
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Streamlined Deployment: Rich test/debug tools simplify validation.
Deliverables
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GDSII layout database with abstracts
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Verilog netlists, STA scripts, and timing libraries (.lib/.db)
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Behavioral simulation models and testbenches
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Complete documentation: integration notes, user guide, and test guidelines
