Description
The 112G SerDes IP Core in 12nm provides high-performance serial connectivity designed for advanced networking, data center, and storage SoCs. Supporting both 112 Gbps PAM4 signaling and 56 Gbps NRZ modes, it offers a balance of performance, power efficiency, and area savings.
This SerDes integrates adaptive equalization, reflection cancellation, and robust CDR to enable long-reach operation over lossy channels, making it ideal for optical modules, backplane links, and chip-to-chip communication. Optimized for port density and low power consumption, it is silicon-proven on the 12nm FinFET process, ensuring a reliable production-ready solution.
Features
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Multi-rate support: 1–56 Gbps (NRZ) and 56–112 Gbps (PAM4).
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Long-reach capable with DFE, FFE, and adaptive equalization.
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Integrated microcontroller for autonomous adaptation and configuration.
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On-chip diagnostics: PRBS generators/checkers, eye stats, BER measurement, loopback modes.
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Silicon proven in 12nm FinFET process technology.
Applications
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Networking switches and routers
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Hyperscale data center interconnects
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Cloud and AI accelerators
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Optical backplane & chip-to-chip communication
Benefits
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Robust Performance: Reliable over challenging and reflective channels.
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Energy Efficient: Optimized power for dense multi-lane deployments.
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Integration Ready: Compact architecture suitable for large SoCs.
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Validated & Proven: Silicon-proven in 12nm, ensuring faster time-to-market.
Deliverables
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GDSII layout with LEF abstracts
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Liberty timing/power models (.lib/.db)
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Post-layout Verilog netlist & SDF
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RTL/behavioral simulation models
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Verification testbenches & scripts
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Documentation: integration guide, user manual, and test guidelines
