Description
The ASA-ML Serdes IP Core in 22nm is a silicon-proven, production-ready physical layer solution designed in compliance with the Automotive SerDes Alliance (ASA) specifications. Built for next-generation in-vehicle networking, this PHY enables high-speed, low-latency data transmission for advanced driver assistance systems (ADAS), autonomous driving platforms, infotainment, and connected vehicle applications.
Engineered on the 22nm process, the PHY is optimized for low power consumption, robust EMI/EMC performance, and scalability across automotive SoC platforms. With its flexible lane configuration and support for bi-directional high-speed serial links, the ASA PHY provides a reliable and future-proof connectivity foundation.
Features
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ASA Standard Compliant PHY for next-generation automotive SerDes links.
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High-speed operation with scalable lane architecture.
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Low latency and low power for real-time in-vehicle data processing.
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Built-in diagnostic and test features for automotive safety compliance.
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Robust EMI/EMC design tailored for harsh automotive environments.
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Silicon-proven on 22nm process node.
Applications
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ADAS (Advanced Driver Assistance Systems)
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Autonomous driving compute platforms
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Automotive infotainment and cockpit systems
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High-resolution cameras, radars, and LiDAR
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In-vehicle networking (IVN)
Benefits
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Automotive Grade Reliability: Qualified for high-performance automotive designs.
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Scalable Performance: Configurable link speeds for multiple automotive use cases.
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Future-Ready: Compliant with ASA standards for long-term ecosystem adoption.
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Ease of Integration: Delivered with complete design kits and integration support.
Deliverables
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GDSII and LEF layout views
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Liberty (.lib/.db) timing and power models
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Netlists with SDF for post-layout verification
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RTL/behavioral simulation models
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Testbenches and validation scripts
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Documentation: user guide, datasheet, and integration notes
