Production Proven, Complex Semiconductor IP Cores

Semiconductor IP Cores


T2M Ethernet 100M/1000M Base-T1 Ethernet PHY IP in 28nm

100M/1000M Base-T1 Ethernet PHY IP in 28nm

Description

The 100M/1000M Base-T1 Ethernet PHY IP Core in 28nm offers a cost-efficient, low-power, and robust Ethernet connectivity solution for single-pair cabling systems. Fully aligned with IEEE 802.3bw (100Base-T1) and IEEE 802.3bp (1000Base-T1) standards, this PHY enables scalable communication at both 100 Mbps and 1 Gbps, making it a perfect fit for automotive networking, industrial automation, and connected devices.
Optimized in the 28nm process node, the PHY achieves a balance between area efficiency and power savings, while ensuring signal integrity through advanced equalization, echo cancellation, and noise tolerance mechanisms. It is silicon-proven and production-ready, ensuring reliable deployment in high-volume SoCs.

Features

  • Standards Support: IEEE 802.3bw (100Base-T1) & IEEE 802.3bp (1000Base-T1).
  • Dual Speed: Supports 100 Mbps & 1 Gbps operation.
  • Process Node: Designed and validated in 28nm for optimized area/power trade-off.
  • Signal Conditioning: Adaptive equalizer, echo cancellation, and jitter suppression.
  • Diagnostics: PRBS pattern generators, loopback modes, and BIST.
  • Interfaces: Compatible with standard MAC interfaces – MII, GMII, RGMII.

Applications

  • Automotive Ethernet: ADAS, infotainment, and autonomous vehicle platforms.
  • Industrial IoT: Low-cost Ethernet for automation, robotics, and sensor systems.
  • Edge & Consumer Devices: Energy-efficient networking backbone.
  • Transportation Systems: EMI-resilient connectivity in rail and avionics.

Benefits

  • Optimized at 28nm: Power and area savings for cost-sensitive designs.
  • Proven Silicon: Ready for deployment in mass production.
  • Flexible Performance: Seamless operation across 100M and 1G speeds.
  • High Reliability: Maintains robust data integrity under noisy environments.
  • Ease of Use: Standard interfaces with clear documentation and support.

Deliverables

  • GDSII with LEF Abstracts
  • Liberty Timing Libraries (.lib/.db)
  • Behavioral Verilog Models with Testbenches
  • Verification Scripts and Test Patterns
  • LVS-Compatible CDL Netlists
  • Datasheet, Integration Notes, and User Guide