Description
The 112G SerDes IP Core built on advanced 5 nm FinFET technology delivers ultra-wideband serial connectivity for modern SoCs, tailored to meet the demands of cloud, data center, and AI infrastructure. Supporting up to 112 Gbps per lane using PAM4 or scalable down to lower speeds via NRZ, this IP delivers best-in-class performance in terms of power, area, and reliability. It features extended long-reach (ELR) capabilities that enable robust communication over lossy or reflective channels.
Features
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Multi-Rate Design: Operates at 56–112 Gbps with PAM4 or 1–56 Gbps with NRZ.
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Optimized for Lossy Channels: Reflection cancellation and advanced DSP enhance signal margin over challenging interconnects.
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High Integration Efficiency: Small area, low power footprint for high port-density applications.
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Autonomous Operation: Integrated microcontroller for self-start, dynamic adaptation, and configuration via MDIO-style interface.
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Advanced Diagnostics: On-chip BIST, PRBS generation/checking, histograms for BER estimation, eye-statistics, and channel estimators support post-deployment tuning and debugging.
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Silicon Proven in 5 nm: Validated on TSMC’s 5 nm node for reliable implementation.
Applications
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High-bandwidth interconnects in data centers and AI platforms
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High-speed optical backplanes and chip-to-chip communication
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Hyperscale networking and traffic-intensive systems
Benefits
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Exceptional Performance Margin: Suitable for long-reach and reflective environments.
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Compact & Energy-Efficient: Ideal for space-constrained and power-sensitive applications.
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Simplified Integration: On-chip microcontroller reduces ASIC host dependency.
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Easy Testing & Debugging: Rich embedded diagnostics streamline validation and optimization.
Deliverables
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GDSII layout files with LEF abstracts
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Verilog post-layout netlist and STA scripts
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Liberty timing models (.lib/.db)
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Comprehensive documentation including verification scripts and integration guide
