Description
The ASA-ML Serdes IP Core in 28nm delivers reliable, high-speed automotive SerDes connectivity designed in full compliance with the Automotive SerDes Alliance (ASA) specifications. Built on a 28nm process, it balances cost efficiency, performance, and robustness, making it a practical solution for automotive OEMs and Tier-1s targeting in-vehicle networking (IVN), ADAS, and autonomous driving systems.
With strong EMI/EMC resilience, low-power operation, and configurable link bandwidths, this PHY is an excellent fit for scalable automotive platforms. It provides seamless interoperability with the ASA ecosystem, ensuring future-proof deployment.
Features
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Fully ASA standards compliant PHY for next-generation automotive links.
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High-speed bidirectional serial communication with configurable lanes.
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Robust EMI/EMC design optimized for 28nm automotive process.
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Low power architecture for energy-efficient in-vehicle integration.
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Built-in self-test (BIST) and diagnostic support.
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Silicon-proven in 28nm technology node.
Applications
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ADAS & autonomous driving compute
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High-resolution cameras, radar, and LiDAR
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Infotainment and cockpit systems
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In-vehicle networking for connected cars
Benefits
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Cost-optimized solution: 28nm node balances price and performance.
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Reliable automotive-grade PHY: Designed for long-term field deployment.
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Flexible integration: Supports diverse in-vehicle data transmission needs.
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Future-ready: Interoperable within ASA ecosystem for evolving automotive standards.
Deliverables
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GDSII & LEF layout views
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Liberty (.lib/.db) timing/power libraries
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Post-layout netlist with SDF
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RTL/behavioral simulation models
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Verification testbenches & scripts
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User manual, datasheet, and integration guidelines
