Production Proven, Complex Semiconductor IP Cores

Semiconductor IP Cores

T2M › SerDes › 32G SerDes PHY IP in 28nm

32G SerDes PHY IP in 28nm

Description

The 32G SerDes IP Core is a high-performance Serializer-Deserializer solution, optimized for advanced SoC integration at 14nm FinFET process nodes. Supporting data rates up to 32 Gbps per channel, this IP is designed to deliver high bandwidth, low power, and low latency serial connectivity for next-generation networking, data center, storage, and high-performance computing applications.
With multi-protocol support, adaptive equalization, and robust clock-data recovery (CDR) mechanisms, the 32G SerDes IP ensures reliable transmission across challenging interconnects, enabling flexible use in standards such as PCIe, Ethernet, Fibre Channel, and proprietary high-speed links. Its silicon-proven architecture ensures rapid deployment, reduced risk, and scalability for future designs.

Features

  • Data Rate Support: Up to 32 Gbps per lane, scalable multi-lane architecture.
  • Standards Compliance: Supports PCIe Gen4, 100G Ethernet, Fibre Channel, OIF-CEI, and custom protocols.
  • Process Node: Available in 14nm FinFET technology.
  • Adaptive Equalization: CTLE, DFE, and TX FIR filtering for optimized signal integrity.
  • Clocking Architecture: Robust CDR with jitter tolerance and spread-spectrum support.
  • Power Optimized: Advanced design techniques ensure low energy per bit.
  • Built-In Diagnostics: BIST, PRBS generation/checking, loopback modes, and eye diagram monitoring.
  • Flexible Interfaces: PIPE, XFI, and standard parallel interfaces for MAC/PHY integration.

Applications

  • Data Center & Cloud Systems – High-speed interconnects for servers, switches, and routers.
  • Networking Infrastructure – 100G/400G Ethernet, optical transport, and metro networks.
  • High-Performance Computing (HPC) – Low-latency chip-to-chip and die-to-die communication.
  • Storage Solutions – Fibre Channel and high-speed NVMe interconnects.
  • Automotive & Industrial – Advanced Ethernet backbones and AI/ML accelerators.

Benefits

  • High Bandwidth Efficiency: Up to 32 Gbps per lane with multi-protocol flexibility.
  • Silicon-Proven Reliability: Reduced risk with production-tested IP.
  • Low Power & Area Optimized: Efficient design for power-sensitive SoCs.
  • Customizable: Configurable architecture supports multiple protocols and system needs.
  • Ease of Integration: Delivered with documentation, models, and test support.

Deliverables

  • GDSII Layout Database with process-specific mapping
  • Liberty Timing Models (.lib/.db) for STA & synthesis
  • Verilog Behavioral Models for simulation
  • Test Benches, PRBS, and Verification Scripts
  • LEF Abstracts for P&R integration
  • CDL Netlists for LVS verification
  • Integration Documentation & Application Notes
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