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16G Multiprotocol Serdes IP Core With Different Interface Protocols For Your High-Speed Interconnect Requirements In 28HPC+ Process Technology Is Available For Immediate Licensing

25 Apr, 2022

T2MIP, the global independent semiconductor IP Cores provider & Technology experts, is pleased to announce the immediate availability of its partner’s 16G Multiprotocol SerDes PHY IP Core in 28HPC+ process node which is silicon proven and in mass production with its superfast data transfer speed, low power and low die area providing a highly reliable system.
 
The 16G Multiprotocol SerDes PHY IP Core supports PCIe 4.0JESD204B, 10G ethernet, rapid IO, and CPRI protocols. This allows the Serdes PHY to be implemented into a diverse range of applications based SoCs. Boasting a Low power and Low Die area, the PHY’s lower power consumption is achieved due to support of additional PLL control, reference clock control, and embedded power gating control. Also, with configurable low power mode, the PHY is widely applicable for various scenarios under different consideration of power consumption.
 
The multiple Protocols allows for the capability of handling various applications such as Wired and Wireless Communications, Data Converter connectivity, Chip-to-Chip interconnect, and Networking. The 16G Multi-Protocol Serdes PHY IP Core has multiple lanes transceiver with data rate from 1Gbps to 16Gbps with the availability of a Transceiver version including both receiver and transmitter. The 16G Serdes PHY has a layered structure able to handle 40bit/ 32bit/ 20bit/ 16bit selectable parallel data bus with the option of Independent per-lane power down control. To compensate for insertion loss Embedded receiver equalization (CTLE and DFE) is used with the help of a Programmable transmit amplitude and a 3-tap feed forward equalizer (FFE).
 
The Serdes IP Core is available for both Flip Chip Package and Wire Bonding Package. The added benefit of an integrated LC-tank PLL and AC coupling, the Core can achieve a spread spectrum clock up to 5000ppm on a Low capacitance ESD structure with ESD (HBM): over 2000V and ESD (CDM): over 250V. The 16G Multiprotocol Serdes PHY IP Core also provides a High Testability feature with a Built-in pattern generator and checker including PRBS and an Internal serial loopback. 
 
The 16G Multiprotocol SerDes PHY IP core has been used in semiconductor industry’s Enterprise computing, storage area networks, Wireless and mobile devices, IoT, Embedded systems, Graphics devices and other Consumer and Industrial uses…
 
In addition to SerDes PHY IP Cores, T2M‘s broad silicon Interface IP Core Portfolio includes USB, HDMI, Display Port, MIPI (CSI, DSI, UniPro, UFS, Soundwire, I3C), DDR, 10/100/1000 Ethernet, V by One, programmable SerDes, SD/eMMCs and many more Controllers and PHYs available in major Fabs in process geometries as small as 7nm. They can also be ported to other foundries and leading-edge processes nodes on request.
 
 
 
 
About T2M: T2MIP is the global independent semiconductor technology experts, supplying complex semiconductor IP Cores, Software, KGD and disruptive technologies enabling accelerated development of your Wearables, IOT, Communications, Storage, Servers, Networking, TV, STB and Satellite SoCs. For more information, please visit: www.t-2-m.com
 
Availability: These Semiconductor Interface IP Cores are available for immediate licensing either stand alone or with pre-integrated Controllers and PHYs. For more information on licensing options and pricing please drop a request / MailTo