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Elevate Your Video And Display Applications With The Multi-Stream Transport Of DisplayPort/eDisplayPort V1.4 Rx PHY IP Cores In 22nm, 28nm And 40nm With Matching Controllers

30 May, 2022

T2MIP, the global independent semiconductor IP Cores provider & Technology experts, is pleased to announce the immediate availability of its partner’s VESA standard eDisplay Port / Display Port v1.4 Rx Controller and matching PHY IP Cores in 22ULP, 28HPC+ and 40LP process nodes which are silicon proven in major Fabs with high efficiency and low power consumption.
eDisplay Port / Display Port v1.4 Rx PHY and Controller IP Cores which was developed to topple the older DVI, VGA and other standards has brought forward new prospects in Display applications. With this DisplayPort version 1.4 compliant Receiver PHY supporting 1.62Gbps (RBR) to 8.1 Gbps (HBR3) bit rate. Equipped with configurable analog characteristics such as integrated 100-ohm termination resistors with common-mode biasing, CDR bandwidth, and Integrated equalizer with tunable strength, at about 1.8V/0.9V power supply makes it powerful, power efficient and superfast.
The eDisplay Port / Display Port v1.4 Rx PHY IP Cores is compliant with eDP version 1.4a / DP version 1.3 and also supports HDCP1.4 and HDCP2.2. The Rx PHY in 22nm, 28nm and 40 nm consists of configurable (4/2/1) link channels and one AUX channel. With support for 1.62Gbps (RBR), 5.4Gbps (HBR2) and 8.1 Gbps (HBR3) bit rate, the DisplayPort IP Cores main link operation with 1 or 2 or 4 lanes Supports both Default and Enhanced Framing Mode. Display Data Connection is interfaced with 18/24-bit RGB digital video output format Master I2C interface, which can also include Interface to external HDCP key storage.
The eDisplay Port / Display Port v1.4 Rx Controller IP Cores with its core function of Forward Error Correction with added benefit of backward compatibility also supports 1.62/2.7/5.4/8.1Gbps (HBR3) bit rate and all recommended link rate. It supports main link operation with 1 or 2 or 4 lanes, which can in turn facilitate support for: • Default and Enhanced Framing Mode • SST mode • Normal and Alternate Scrambler Seed Reset. Our IP Core also comes with Configuration registers programmable via AMBA interface.
The eDisplay Port / Display Port v1.4 Rx Controller and PHY IP Cores with a clear lossless video compression technology that multiplies the DisplayPort data transfer capacity has been used in semiconductor industry’s computing, digital displays, monitors, TVs, Automotive and other consumer electronics. ….
In addition to Display Port/eDisplay Port IP Cores, T2M‘s broad silicon Interface IP Core Portfolio includes USB, HDMI, MIPI (CSI, DSI, UniPro, UFS, Soundwire, I3C), PCIe, DDR, 10/100/1000 Ethernet, V by One, programmable SerDes, Serial ATA and many more, available in major Fabs in process geometries as small as 7nm. They can also be ported to other foundries and leading-edge processes nodes on request..
About T2M: T2MIP is the global independent semiconductor technology experts, supplying complex semiconductor IP Cores, Software, KGD and disruptive technologies enabling accelerated development of your Wearables, IOT, Communications, Storage, Servers, Networking, TV, STB and Satellite SoCs. For more information, please visit:
Availability: These Semiconductor Interface IP Cores are available for immediate licensing either stand alone or with pre-integrated Controllers and PHYs. For more information on licensing options and pricing please drop a request / MailTo