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Introducing High-Speed Fractional PLL IP Cores With SSC That Offers Exceptional Features In Different Process Technologies

24 Apr, 2023

T2MIP, the global independent semiconductor IP Cores provider & Technology experts, is pleased to announce the availability of its partner’s High-Speed Fractional PLL IP Cores with SSC ranging from 22nm to 180nm process technology. This high performance PLL IP cores can be used in wide range of applications.
This High-Speed Fractional PLL with SSC IP cores is a combination of two key components: a Fractional Phase-Locked Loop (PLL) and a Spread Spectrum Clock (SSC) generator. PLL with SSC (spread-spectrum clocking) is a crucial component in modern electronic systems. This core offers several advantages that includes, reduced electromagnetic interference, improved clock stability, and reduced power consumption. As technology nodes continue to shrink, the demand for high-speed fractional PLLs with SSC has increased:
A PLL is used to generate an output signal with a frequency which is multiple of a reference signal. The PLL locks on the reference signal and generates an output signal that is phase-locked to the input signal, with a stable and precise frequency output. Fractional PLLs are designed to provide even greater precision and accuracy by allowing fractional values for the frequency multiplication ratio, enabling more precise control over the output frequency.
On the other hand, an SSC generator is a circuit that modulates the frequency of a clock signal over a range of frequencies, typically by spreading the energy of the clock signal across a wider range of frequencies. This modulation technique is used to reduce electromagnetic interference (EMI) and improve signal integrity.
Combination of Fractional PLL and SSC generator creates an IC design that provides high-speed clock generation with improved signal integrity and reduced EMI. This technology is commonly used in high-speed digital communication systems, such as wireless and wired networks, and also other applications where precise clocking and signal integrity are critical.
The high-speed fractional PLL with SSC is available for immediate licence from 22nm to 180nm technology node. T2M offers a range of deliverables, including GDSII layout, CDL netlist (MG Calibre compatible), functional Verilog model, liberty timing models (.lib), and LEF. Additionally, application notes are also provided to assist designers in using these components effectively.
Availability: These Semiconductor Interface IP Cores are available for immediate licensing either stand-alone or with pre-integrated Controllers and PHYs. For more information on licensing options and pricing please drop a request / MailTo
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