T2MIP, the global independent semiconductor IP Cores provider & Technology experts, is pleased to announce the immediate availability of its partner’s MIPI Alliance Standard MIPI D-PHY v1.2 Tx IP Core in 22nm process node and its matching MIPI DSI-2 Tx v1.1 Controller IP Core for all types of Display and Camera applications. The D-PHY IP Core together with the DSI-2 Controller IP boasts flexibility, high speed, power efficiency and low cost.

 

The MIPI D-PHY Analog Tx IP Core uses PPI interface and is fully compliant to the D-PHY specification version 1.2. It supports the MIPI Camera Serial Interface (CSI-2) and Display Serial Interface (DSI protocols). The D-PHY consists of an analog front end to generate and receive the electrical level signals, and a digital back end to control the I/O functions. The D-PHY has an internal termination resistor with auto-calibration and includes a PLL, a Clock Lane and four Data Lane for MIPI DSI data transmission. The D-PHY in 22nm process node can also be used as a 5V tolerance GPIO bank. It moderates synchronous transfer at high-speed mode with a bit rate of 80-2500 Mb/s and asynchronous transfer at low power mode with a bit rate of 10 Mb/s. It also supports ultra-low power mode, high speed mode and escape mode making it highly flexible and power efficient. Data lanes support transfer of data in high-speed mode with error detection mechanism for sequence errors and contentions. Configurable skew option for each Clock and Data lanes makes it easily controllable with added feature of testability for TX, RX and PLL.