T2MIP, the global independent semiconductor IP Cores provider & Technology experts, is pleased to announce the availability of its partner’s silicon and production-proven 14-bit Wideband Time-Interleaved Pipeline ADC IP cores supporting 4.32 Gsps sampling speed in 28nm FDSOI process with full modification rights and unlimited usage. The 14-bit, 4.32Gbps Pipeline ADC IP Cores, extracted from a Production Chipset, supports 60dB Signal Noise Ratio (SNR) with input frequencies ranging from 54MHz to 1.7GHz. They are used in a variety of applications, including audio applications, microcontrollers, high-speed STB, Wi-Fi, automotive, radar, and 5G applications.
The ADC IP Cores includes two internal power supply regulators (LDO) for the analog part:
A 1.1v LDO with an external decoupling capacitor to reach a high-power rejection ratio,
A 1.5v LDO with an internal capacitor for the input buffer and biasing
The digital part is supplied by the external 1.0V..
This ultra-high-speed wide-band Analog-to-Digital Converter IP cores, is based on 16 Time-Interleaved Pipeline sub-ADC followed by a digital correction algorithm for gain, offset, and skew correction. The differential input is terminated by a 100 Ohms resistor (100 Ohms differential) and followed by an input buffer driving the sub-ADC. The signal amplitude is 1Vpp differential. The analog source driving the ADC should be coupled to the input pins with two external capacitors of 1nF minimum. The input common models are generated internally:
ADC IP Cores is a mixed-signal system made up of a comparator, switch-capacitor circuits, biassing circuits, bandgap voltage reference, sample and hold amplifier (SHA), and multiplying digital-to-analog converter (MDAC). It connects all the specs at the circuit and system levels. A pipeline ADC IP Core is designed using two or more low resolution Flash ADCs. The architecture is divided into number of stages where each stage consists of Sample and Hold circuit. This circuit samples the analog signal and holds the sampled value for a short interval of time. This signal is fed to Flash ADC to get the binary output. The generated binary outputs from each stage is then time-aligned (Pipelined) to the Shift Register and further undergoes error detection and correction using Digital Error Correction Logic to obtain the final Binary output.
T2M’s extensive range of wireless IP cores also includes Bluetooth Dual mode v5.2 RF Transceiver IP Cores in 22nm ULL, BLE v5.2 / 15.4 (0.5mm2) RF Transceiver IP Cores in 40/55nm, NB-IoT/Cat M UE RF Transceiver IP Cores in 40ULP, and Sub6 GHz RF Transceiver IP Cores, all of which can be ported.
Availability: This Analog Data convertor IP cores is available for immediate licensing. For further information on licensing options and pricing please drop a request at contact.
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