T2MIP, the global independent semiconductor IP Cores provider & Technology experts, is pleased to announce the immediate availability of its partner’s Silicon Proven and mature USB 3.2 Gen2x2 Host & Device Controllers along with PHY IP Corein 28nm HPC+ process technology. This USB solution has an exceptional track record of large-scale production in a wide variety of devices and is a bedrock for transmission of data for industrial and consumer applications.
USB 3.2 Gen 2x2 Host & Device Controller & PHY IP core in 28nm HPC+ essentially handles 2-lanes each 10GBps. USB 3.2 Host and Device Controllers are highly configurable core and implements the USB 3.2 Host and Device functionality respectively that can be interfaced with the USB 3.2 Gen2x2 PHY for a superfast and reliant total solution. The USB 3.2 Gen2x2 core is architected with a high-performance DMA engine based on USB3.2 specification and is carefully partitioned to support standard power management schemes which include extensive clock gating and multiple power wells for aggressive power savings required for mobile and handheld applications:
USB 3.2 Gen2x2 Host & Device Controller IP has a very simple application interface which can be easily adapted to standard on-chip-bus interfaces such as AXI, AHB, OCP as well as other standard interconnects making it easy to be integrated in a wide range of applications. It also has a dedicated PHY Type-C connector Interface for identifying Type-C specific features and can be configured to support all types of USB transfers like Bulk, Interrupt and Isochronous. Both Host and Device parts has full support for all low power features of the USB Specification supporting Suspend, Remote Wakeup and USB 3.0/2.0 Link Power Management States.
USB 3.2 Gen2x2 PHY IP Core in 28nm HPC+ process technology is compliant with USB 3.2 and 2.0 electrical specifications and supports both the UTMI+ and PIPE4.0 specifications with the 3.2 Gen2X2 host and peripheral applications being supported up to 20Gbps The Physical layer incorporates an active switch to support bi-directional plug-in and particular functionalities to support the USB Type-C connector. Boasting one of the smallest USB 3.2 Gen2x2 process and clock inputs from 25MHz crystal oscillator and external clock sources from the core, the IP also maintains a very low power consumption factor. Additional 3-Tap FIR Equalization for TX and CTLE+1-Tap DFE for RX makes it a powerful and lossless technology.
USB 3.2 Gen 2x2 Host & Device Controllers & PHY IP core in 28HPC+ has been used in many semiconductor devices: Scanners, Digital cameras, Removable media drives, Mass storage devices, Display and docking applications, Cloud computing, Automotive applications, Consumer applications, Smartphones and other industrial uses.
In addition to USB 3.2 IP Core, T2M ‘s broad silicon Interface IP Core Portfolio includes HDMI, Display Port, MIPI (CSI, DSI UniPro, UFS, RFFE, I3C), PCIe, DDR, 1G Ethernet, V-by-One, programmable SerDes, OnFi and many more, available in major Fabs in process geometries as small as 7nm. They can also be ported to other foundries and leading-edge processes nodes on request.
Availability: These Semiconductor Interface IP Cores are available for immediate licensing either stand alone or with pre-integrated Controllers and PHYs. For more information on licensing options and pricing please drop a request at contact.
About T2M: T2MIP is the global independent semiconductor technology experts, supplying complex semiconductor IP Cores, Software, KGD and disruptive technologies enabling accelerated development of your Wearables, IOT, Communications, Storage, Servers, Networking, TV, STB and Satellite SoCs. For more information, please visit: www.t-2-m.com
