ATSC3 Demodulator and Decoder IP
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his ATSC Demodulator IP is extarted from production chip and silicon proven IP core. It integrates a digital terrestrial (ATSC) receiver (8VSB demodulation and FEC) and a downstream interactive out-of-band (OOB) receiver (QPSK Demodulation).
Fully compliant with A/321 and A/322 ATSC3.0 standard -Support FDM / TDM / LDM -Maximum 64 PLPs (with extra TINT memory) Leading all three plug-fest test with our equipment's -1st : 2015.11, Sanghai, China -2nd : 2016.3, Baltimore, US -3rd : 2016.10, Jeju, Korea (we host this with ETRI). Lab Modulator: Used as a test transmitter in LAB. Transmitter With DPD functions and 1K watt transmit power amp. Ready to sell, already tested in Korean sites, Professional Receiver, Used as a reference in performance, Used as outdoor field test. Master Antenna TV chipset: Equipment for relaying ATSC3.0 baseband frame, We have made the TX and RX chipsets separately, Commercialized in Korea already.
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- Tested in real broadcasting environment.
- KBS/MBC/SBS are using our equipment for field-measurement
- Conducted field test several times with MBC/SBS
- Conducted a plug-fest lead by government institution with KBS
- Well balanced S/W and H/W partitioning
- Easy to upgrade or add new feature
- Cortex M3 are sufficient to control
- Very highly optimized
- Fitted in single mid-sided FPGA(Virtex7 690T)
- Single port ram are mainly used for silicon area
- Ready to ASIC
- Not using any other IP
- Need only memory conversion to ASIC
Benefits
- Using high performance CPU
- Optimized for FPGA
- Fitted in single FPGA (Virtex7-690T)
- Fully featured of measurement equipment
- Support FDM/TDM/LDM
Applications
- TV
- STB