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    USB 1.1 DEVICE CONTROLLER

    OverviewFeaturesRequest Datasheet

    USB 1.1 controller is designed for compliance with USB2.0 specification Revision 2.0 and all associated ECN’s.

    USB 1.1 Device controller, can optionally include a proprietary high performance DMA engine for moving USB payloads. The register interface of the DMA Engine is very simple allowing device side class specific function drivers to be implemented easily. Reference mass storage class device side function drivers are made available to all licensees. All buffering associated with the DMA Engine are configurable based on latency and performance requirements.

    USB 1.1 Device controller can optionally include a proprietary EP0 processor block for managing all Standard Requests directed to the control endpoint minimizing software development overhead. Class and Vendor specific requests directed to Control endpoint are routed via the DMA engine to software for processing.

    Optionally, the controller can be provided with no DMA Engine and no buffering and operates in a cut-through mode forwarding and receiving USB payloads and managing only the USB protocol. Customer may in this case implement its own differentiated DMA Engine. Optionally, a simple transmit and receive buffer is included in this configuration which can be accessed by software over the slave register access interface which is typically AHB. This option results in very low footprint hardware which can be used in cases where the software can completely manage the USB traffic – including the sequencing of the USB transactions.

    Design Attributes:

    • Highly modular and configurable design
    • Layered architecture
    • Fully synchronous design
    • Supports both sync and async reset
    • Clearly de-marked clock domains
    • Extensive clock gating support
    • Multiple Power Well Support
    • Software control for key features
    Power Management Support:
    • Supports USB Suspend state and supports remote wakeup devices.
    • Supports all FS USB Link Power Management States – L1, L2.
    • Supports system low power and related system states such as Sleep, Hibernate, Warm/ Cold boot etc.
    • Support for clock gating and multi-power-well support.
     
    • USB 1.1 Device Controller can be configured to support all types of USB transfers – Bulk, Interrupt and Isochronous.
    • Allows dynamic configuration to support configurable number of endpoints, interfaces, alternate interfaces and configurations.
    • USB 1.1 Device Controller can be configured to support any combinations of USB 1.1 interface speeds – LS(1.5 Mbps), FS (12.0 Mbps). Eg combinations are LS Only, FS Only, LS and FS Only.
    • USB 1.1 Device Controller has full support for all low power features of the USB Specification supporting Suspend and Remote Wakeup and Link Power Management states – L1, L2.
    • USB Controllers have been Silicon Proven in wide range of products such as Graphics Controller, Flash Storage Controllers, SATA Bridges with support for Bulk Streaming, Embedded Hosts, Docking Stations, Mobile Application Processors, Smart TV, Hubs.
    Product Package:
    • Configurable RTL Code
    • HDL based test bench and behavioral models
    • Test cases
    • Protocol checkers, bus watchers and performance monitors
    • Configurable synthesis shell
    • Documentation
    • Design Guide
    • Verification Guide
    • Synthesis Guide
    • FPGA Platform for Pre-Tape-out Validation
    Protocol Layer Feature:
    • Supports Interrupt / Bulk / Isochronous / Control Transfers.
    • Supports configurable number of interfaces, configurations, and alternate settings while operating in device mode.
    • Supports configurable endpoint characteristics – for Maximum Packet Size, Endpoint Type etc.
    • CRC16 checking and generation for FS/LS data packets.
    • CRC5 generation and checking for Tokens.
    • Supports preamble for LS transfers while operating in Host Mode.
    • Supports Protocol Layer Error Handling.
    • Provides prioritized scheduling for periodic endpoints.
    • Separate round robin scheduling algorithm within Periodic and Non-periodic endpoints pipes.

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