USB 2.0 OTG Controller IP
We provide highly configurable USB 2.0 OTG/dual-role controller IP Core. Our host, device, and hub are silicon realized, and also USB-IF certified by customers. We also provide highly configurable and scalable USB 2.0 OTG/dual-role controller IP Core for a wide range of applications.
This USB 2.0 OTG controller is compliant with USB2.0 specifications Revision 2.0 and all associated ECN’s, as well as USB OTG EH 2 Revision 1.1a and all associated ECN’s. While operating in host mode, it is compliant with either xHCI, EHCI/OHCI, based on the configurations selected. This allows standard Windows, Linux, Android drivers to be reused, minimizing software development overheads and the risks involved with custom bare metal driver solutions. The solution’s physical interface is compliant with either ULPI+ or 8/16 bits UTMI PLUS Level3 specifications, while the system interface is compliant with either AHB and/or AXI interface – enabling easy integration. We offer optional custom bridges that can be bundle into the service offering. Additionally USB 2.0 OTG controller can support either one device connected directly to its port or multiple devices connected via hubs, in host mode. The USB 2.0 OTG controller could include an high-performance DMA engine when operating in device mode, used for moving USB payloads. The DMA Engine has a simple register interface, allowing device-side class specific function drivers to be easily implemented. This DMA engine can also be reused for host mode operations, and custom bare metal drivers can be configured to manage the connected devices. This optimizes hardware and software footprint significantly. All buffering linked to the DMA engine is configurable, based on the customer’s latency and performance requirements. Class and vendor-specific requests directed to control endpoint are routed to software via the DMA engine for processing. Further, we provide all our licensees access to reference mass storage-class device side function drivers.
The USB 2.0 OTG controller can include an EP0 processor block (proprietary) for managing all standard requests directed to the control endpoint when operating in device mode, reducing software development overheads. Optionally, the controller can be provided with no DMA engine and no buffering, operating in a cut-through mode, forwarding and receiving USB payloads, and managing only the USB protocol. In this case, the customer can implement their own differentiated DMA Engine. Optionally, a simple transmit and receive buffer is included in this configuration, accessible via software over the slave register access interface (typically AHB). This option results in very low footprint hardware, useful for cases where the software can completely manage USB traffic – including the sequencing of the USB transactions.
- The USB 2.0 OTG controller can be configured to support all types of USB transfers – bulk, interrupt and isochronous. In device mode, it can be dynamically configured to support a configurable number of endpoints, interfaces, alternate interfaces, and settings.
- The USB 2.0 OTG controller can be configured to support any combination of USB 2.0 interface speeds – LS (1.5 Mbps), FS (12.0 Mbps), HS (480 Mbps). Sample combinations are LS only, FS only, HS only, LS and FS only, or FS and HS only.
- The USB 2.0 OTG controller has full support for all low power features of USB specifications, supporting suspend, remote wakeup and Link Power Management states – L1, L2.
- The USB 2.0 OTG controller has full support for all test modes features which is required for obtaining USB-IF certification.
- The USB 2.0 OTG controller has full support for OTG features such as SRP, HNP and ADP along with software configurable options to turn these features on/off.
- Our USB controllers have been silicon proven in a wide range of products such as graphics controller, flash storage controllers, SATA bridges with support for bulk streaming, embedded hosts, docking stations, mobile application processors, smart TV, or hubs.
- Highly modular and configurable design
- Layered architecture
- Fully-synchronous design
- Support for both sync and async reset
- Clearly demarcated clock domains
- Extensive clock gating support
- Multiple power well support
- Software control for key features
- Graphics controller
- Flash storage controller
- SATA bridges with support for bulk streaming
- Embedded hosts
- Docking stations
- Mobile application processors
- Smart TV
- Configurable RTL Code
- HDL-based test bench and behavioral models
- Test cases
- Protocol checkers, bus watchers, and performance monitors
- Configurable synthesis shell
- Design guide
- Verification guide
- Synthesis guide
- FPGA platform for pre-tape-out validation
- Reference firmware