JESD204B interface provides full support for the JESD204B synchronous serial interface, compatible with JESD204B.01 version specification. Through its compatibility, it provides a simple interface to a wide range of low-cost devices. JESD204B Transmitter IIP is proven in FPGA environment. The host interface of the JESD204B can be simple interface or can be AHB, AHB-Lite, APB, AXI, AXILite, Tilelink, OCP, VCI, Avalon, PLB, Wishbone or Custom protocol. JESD204B Transmitter IIP is supported natively in Verilog and VHDL.
Compliant with JESD204 specification JESD204A, JESD204B.01.
Full JESD204B transmit functionality.
Supports data rate upto 12.5 Gbps.
Supports programmable clock frequency up to 12.5 GHz.
Supports up to Subclass 0, 1, 2.
Supports up to Version A and B.
Supports 1 to 8 lanes.
Supports 1 to 8 converters per transmitter.
Supports frame sizes of 1,2,4,8 and 16 octets per frame.
Supports 1 to 32 bit data width per converter.
Supports CF = 0 and 1 control words per frame clock period per link.
Supports 0 to 3 control bits per sample.
Supports 1 to 8 samples per converter.
Supports 1 to 32 frames per multiframe.
Supports 4, 8, 12, 16, 20, 24, 28 and 32 bits per sample.
Supports 0 to 15 bank ID – extension to DID.
Supports 0 to 255 device identification number.
Supports 0 to 7 lane identification number.
Supports different Serdes interfaces 10,20,40,60 bits and custom bits per lane.
Continuous sequence of a scrambled jitter pattern (JSPAT) and modified random pattern (modified RPAT).
Continuous sequence of either /D21.5/ or /K28.5/ characters for code group synchronization.
Repeated transmission of a lane alignment sequence, preceded by a code group synchronization sequence.