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MIPI D-PHY IP Cores Along With MIPI DSI Controller IP Cores For Both Tx & Rx Is Available For Immediate Licensing For High-performance, Cost-optimized Cameras And Displays !!

16 Aug, 2022

T2MIP, the global independent semiconductor IP Cores provider & Technology experts, is pleased to announce the immediate availability of its partner’s Silicon Proven and mature MIPI D-PHY Tx-Rx IP Core in major Fabs and Nodes as small as 7nm along with matching MIPI DSI Tx-Rx Controller IP Core. These MIPI Cores has been in Production in multiple chipsets with superspeed Display interface for High quality resolutions upto 4K.
MIPI D-PHY Tx-Rx IP Core along with MIPI DSI Tx-Rx Controller IP Core is an interface between a display or any other data interface, and a host processor baseband application engine is defined by the MIPI Alliance, which lays down a series of modules required in a MIPI compliant product. It is fully compliant to the D-PHY specification version 1.2 and MIPI DSI-2 Standard v0.8.x. The total D-PHY solution has a high-density stability capacity making it a viable solution to integrate and implement in a varied range of applications.
D-PHY is a Physical Layer with one clock lane and 4 data lanes and consists of an analog front end to generate and receive the electrical level signals, and a digital back end to control the I/O functions with an Internal termination resistor for auto calibration. With a support for standard PPI interface compliant to MIPI Specification the D-PHY supports ultra-low power mode, high-speed mode and escape mode, which can support synchronous transfer at high-speed mode with a bit rate of 80-2500 Mb/s and asynchronous transfer at low power mode with a bit rate of 10 Mb/s. Error detection mechanism for sequence errors and contentions, Configurable skew option, 3V tolerance GPIO and a DC Coupling ensures a reliable power consumption flow and a Solid yet flexible solution.
The MIPI DSI Tx-Rx Controller IP Core is able to handle up to 2.5 Gbps per data lane of D-PHY (V2.0), 10Gbps in 4 Lanes which is made possible by its Programmable Data Lane Configuration. Its highly modular design also allows for features such as Forward and reverse communication, and support for command and video mode, burst and non-burst modes, pulse and event modes. It also boasts a Layered architecture with varied Color modes: 16, 18, 24 and 36 bpp and support for Display Stream Compression (DSC).
MIPI D-PHY Tx-Rx IP core along with MIPI DSI Tx-Rx Controller IP core has been used in semiconductor industry’s Smartphones, Surveillance cameras, Automotive Camera, Smart watch displays, digital TVs, handheld computers, personal computers, and other industrial uses….
In addition to MIPI D-PHY IP Core, T2M ‘s broad silicon Interface IP Core Portfolio includes USB, HDMI, Display Port, MIPI (CSI, UniPro, UFS, RFFE, I3C), PCIe, DDR, 1G Ethernet, V-by-One, programmable SerDes, OnFi and many more, available in major Fabs in process geometries as small as 7nm. They can also be ported to other foundries and leading-edge processes nodes on request.
About T2M: T2MIP is the global independent semiconductor technology experts, supplying complex semiconductor IP Cores, Software, KGD and disruptive technologies enabling accelerated development of your Wearables, IOT, Communications, Storage, Servers, Networking, TV, STB and Satellite SoCs. For more information, please visit:
Availability: These Semiconductor Interface IP Cores are available for immediate licensing either stand alone or with pre-integrated Controllers and PHYs. For more information on licensing options and pricing please drop a request at / MailTo