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USB 3.0 PHY IP Cores In 16FFC Process Technology With High-performance Backplane Interconnect Licensed To A Chinese Company For Multimedia SoC Application

09 May, 2022

T2MIP, the global independent semiconductor IP Cores provider & Technology experts, is pleased to announce the licensing of its partner’s USB 3.0 PHY IP with matching Controller IP Cores which is silicon proven and in mass production, to a Chinese company for their High-performance multimedia SoC.
 
USB 3.0 PHY IP Cores in 16FFC is a transceiver which is provided for peripheral devices. The PHY is compliant with the USB 3.0 (USB SuperSpeed), USB 2.0 PIPE and UTMI specifications. The USB 3.0 PHY IP Cores transceiver is optimized for low power consumption and minimal die area without sacrificing performance and high data throughput. The USB 3.0 PHY IP Cores comprises a complete on-chip physical transceiver solution with Electrostatic Discharge (ESD) protection, built-in self-test module with embedded jitter injection, and a dynamic equalization circuit that ensures full support for high-performance designs.
 
 
Compliant with Universal Serial Bus 3.0 Specification the USB 3.0 PHY IP Cores in 16FFC, supports 5.0GT/s and 2.5GT/s serial data transmission rates and is also compliant with PIPE 3.1. The 16FFC process technology is also backward compatible with support for High-speed data transfer rate of 480 Mbps and Full-speed data transfer rate of 12 Mbps. With the support for 16-bit/ 32-bit parallel interface when encode/decode enabled and 20-bit when encode/decode bypassed the IP Cores has low jitter automatically calibrated oscillator for crystal-less mode.
 
Additional support of the Build-In-Self-Test (BIST) mode for low-cost TEG/ATE testing and flexible reference clock frequency makes the IP Cores highly reliable and is able to achieve a Spread-Spectrum clock (SSC) generation and receiving of 5000ppm to 0ppm. The IP Cores also boasts a low IP area and low power consumption due to programmable transmit amplitude and De-emphasis, Low Frequency Periodic Signalling (LFPS) generation and detection, and a highly efficient L1 sub-state power management system.
 
USB 3.0 PHY IP Core in 16FFC process technology along with USB 3.0 Host/Device/Hub/OTG Controller IP Cores are available independently or pre-integrated as a fully validated and integrated solution. The IP Core has been used in semiconductor industry’s Cellular Electronics, PC, Data storage (SSDs), Multimedia Devices and other Consumer Electronic products worldwide.
 
In addition to USB 3.0 PHY IP Cores in 16FFC process nodes, T2M ‘s broad silicon Interface IP Cores Portfolio includes other versions of USB, PCIe, Serial ATA, HDMI, Display Port, MIPI, DDR, 10/100/1000 Ethernet, V by One, programmable SerDes, SD/eMMC and many more Controllers with matching PHYs, available in major Fabs in process geometries as small as 7nm. They can also be ported to other foundries and leading-edge processes nodes on request.
 
About T2M: T2MIP is the global independent semiconductor technology experts, supplying complex semiconductor IP Cores, Software, KGD and disruptive technologies enabling accelerated development of your Wearables, IOT, Communications, Storage, Servers, Networking, TV, STB and Satellite SoCs. For more information, please visit: www.t-2-m.com
 
Availability: These Semiconductor Interface IP Cores are available for immediate licensing either stand alone or with pre-integrated Controllers and PHYs. For more information on licensing options and pricing please drop a request / MailTo