Production Proven, Complex Semiconductor IP Cores

IP Cores



Description and Features

This DDR (Double Data Rate) PHY IP supports DDR3/DDR3L/DDR4, provides low latency, and enables up to 1600Mbps throughput. The PHY IP is silicon proven and designed for ease of integration and faster time-to market. The DDR IP is compliant with the latest JEDEC standards and is silicon proven.

The DDR PHY is interface between DDR controller and SDRAM. The DDR controller is used to control DRAM devices as well as to access the data stored on these devices. Provide multiple AXI interface for AXI master and support DFI standard for DDR PHY to support DDR4/3, data rate 1600Mbps, X8/X16, four ranks, Write leveling, Data training, low power mode and standby mode. The DDR PHY is used to control DRAM devices to access the data stored in these devices, provide SSTL135, POD12 and LVSTL interfaces for DDR3L, DDR4 and DDR3.

Optimized for high performance, low latency, low area, low power, and ease of integration, the DDR4, DDR3, DDR3L PHY is provided as a hard DDR PHY that is primarily delivered as GDSII including integrated application-specific DDR4, DDR3, DDR3L I/Os. Supporting the GDSII-based PHY is the RTL-based PHY. The DDR4, DDR3, DDR3L PHY includes a DFI 4.0 interface to the memory controller and can be combined controllers for a complete DDR interface solution.


  • Supported DRAM type: DDR3L/DDR4/LPDDR4
  • Maximum controller clock frequency of 400MHz resulting in maximum DRAM data rate of 1866Mbps
  • Interface: SSTL135/POD12/LVSTL
  • Data path width scales in 32-bit increment
  • Four modules for flexible configuration: CA/DQ_X16/DQ_X8/ZQ, Programmable output impedance (DS)
  • Programmable on-die termination (ODT)
  • Core power:0.9V, I/O power (VDDQ):1.5V/1.35V/1.2V, RX power:1.8V
  • ESD: 2KV/HBM, 200V/MM, 500V/CDM
  • Support ZQ calibration
  • Support 8 ranks
  • Support write-leveling, CBT
  • Support PHY internal VREFDQ auto decision
  • Per-bit deskew in read and write datapath
  • Supported metal scheme: 1P7M_1C