Your Complex IP Core Partner

    USB 3.1 Hub Controller IP

    OverviewFeaturesRequest Datasheet

    USB 3.1 Hub controller is a highly configurable core and implements the USB 3.1 Hub functionality that can be interfaced with third party USB 3.1PHY’s. USB3.1 Hub controller core is part of USB3.0 family of cores.The core leverages GDA’s design expertise from its high speed interconnect family of IP’s including PCI Express, Serial Rapid IO and Hypertransport.

    This Hub Controller core can be configured to support upto 15 downstream ports. This Hub Controller core supports all defined USB 3.1 power states. The design is carefully partitioned to support standard power management schemes. Optionally, it can be configured to manage power mode transitions of the controller and the USB 3.1 PHY for aggressive power savings required for bus powered hubs. The controller's simple, configurable and layered architecture is independent of application logic, PHY designs, implementation tools and, most importantly, the target technology.

      usb-3.1-hub-controller-ip-silicon-proven-ip-core-provider-in-taiwan  
    t2m-design-reuse t2m-chipestimate t2m-anysilicon
     
    • Compliant with USB3.1 Specification Version 1.
    • Configurable number of downstream ports
    • Configurable Core Frequency
    • Configurable Internal datapath width: 32, 64, or 128 bits
    • Compliant with standard USB 3.1 PHY Interface
    • Configurable PHY Interface width: 8, 16, or 32 bits
    • Efficient buffering scheme for forwarding packets through hub with minimal latency
    • Supports Bus and Self Powered Hub implementations
    • Supports PTM.
    • Supports SCD/LBPM LFPS messages.
    • Supports Type 2 Header buffers.
    • Supports TP reordeirng.
    • USB 3.1 low power states support
    • Support for various Hardware and
    • Software Configurability regarding Core characteristics
    • Register Interface for internal Register Access
    Benefits
    • Highly modular and configurable design
    • Layered architecture
    • Fully synchronous design
    • Supports both sync and async reset
    • Clearly demarked clock domains
    • Software control for key features
    • Master and slave loop backs for debug
    • Aggressive power management
    Applications
    • Automotive
    • Smartphones
    • Tablets
    • Notebooks
    • Gaming
    • Digital cameras and camcorders
    • Storage
    • Wireless communication
    • Set-top boxes
    • Smart TVs and digital TVs
    • Chip-to-chip low-power interconnects
    Deliverables
    • Configurable RTL code
    • HDL-based test bench and behavioral models
    • Test cases
    • Protocol checkers, bus watchers, and performance monitors
    • Configurable synthesis shell
    • Design guide
    • Verification guide
    • Synthesis guide
    • FPGA platform for pre-tape-out validation
    • Reference firmware

      Fill the form below, to receive the product datasheet in your inbox