USB 4.0 Hub Controller IP
The USB 4.0 Hub controller IP is a highly configurable core and implements the USB 4.0 Hub functionality that can be interfaced with third party USB 4.0 PHY's. The USB 4.0 Hub IP core is latest development that enables designers in the PC, mobile, consumer and communication markets to bring significant power and performance enhancements to the popular USB standard while offering backwards compatibility with billions of USB-enabled devices currently in the market. It is validated using FPGA prototype with industry standard PHYs.
- Configurable Number of Downstream USBv4 Ports
- Optional support for DP Source Adaptor
- Optional support for PCIe Down Adaptor
- Optionally a reference firmware running on micorblaze for emulating connection manager for very simple topology.
- Supports USB4 Gen 2x2 (20 Gbps) and USB4 Gen 3x2 (40 Gbps) Links.
- Optional support for thunderbolt Gen 2 (10.3125 Gbps) & Gen 3 (20.625 Gbps) rates.
- Optional bypass mode to support native USB v3.2
- Support for Alt Mode and Billboard class via USB2 controller.
- System Master Interface : 64 / 128 bit AXI Interface
- System Slave Interface : 32 / 64 AHB/AXI Slave Interface
- USB v4 Phy Interface : 40 / 80 bit PIPE 5.1 SERDES I/F
- Side band Channel PHY Interface : Serial I/F
- USB 2 PHY Interface : UTMI / ULPI I/F
- USB 4.0 increases data rates up to a minimum of 20Gbps (40Gbps is also supported)
- USB 4.0 Device is virtually identical in protocol and thus retaining backwards compatibility with older versions 3.2,3.0, 2.0
- Supports PIPE and UTMI+ PHY interfaces
- Architectural features reduce power consumption
- Optimized Host controller IP designed to achieve power boost
- Consumer applications
- Mass storage devices
- Data Centers
- Communication applications
- Display and docking applications
- Cloud computing
- Automotive applications
- Configurable RTL Code
- HDL based test bench and behavioral models
- Test cases
- Protocol checkers, bus watchers and performance monitors
- Configurable synthesis shell
- Design Guide
- Verification Guide
- Synthesis Guide
- FPGA Platform for Pre-Tap