The combination PHY is SATA (Serial ATA) compliant with SATA 3.0 Specification, PCIe (Peripheral Component Interconnect Express) compliant with PIPE interface protocol, and USB (USB 3.0, USB 2.0) compliant (USB High-speed and Full speed). Supporting additional internal power gating, reference clock control, and PLL control helps reduce power consumption. The PHY is also very helpful for a range of situations under varied considerations of power consumption because of the adaptability of the aforementioned low power mode choice.
Compatible with PCIe/USB3/SATA base Specification
Fully compatible with PIPE3.1 interface specification
Data rate configurable to 1.5G/2.5G/3G/5G/6G for different application
Support 16-bit or 32-bit parallel interface when encode/decode enabled
Support 20-bit parallel interface when encode/decode bypassed
Support flexible reference clock frequency
Support 100MHz differential reference clock input or output (optional with SSC) in PCIe Mode
Support Spread-Spectrum clock (SSC) generation and receiving from 5000ppm to 0ppm
Support programmable transmit amplitude and De-emphasis
Support TX detect RX function in PCIe and USB3.0 Mode
Support Beacon signal generation and detection in PCIe Mode
Support Low Frequency Periodic Signaling (LFPS) generation and detection in USB3.0 Mode
Support COMWAKE, COMINIT and COMRESET (OOB) generation and detection in SATA Mode
Support L1 sub-state power management
Support RX low latency mode in SATA operation mode
Support Loopback BERT and Multiple Pattern BIST Mode
HPC Plus 0.9V/1.8V 1P8M
ESD:HBM/MM/CDM/LatchUp2000V/200V/500V/100mA
Silicon Proven in SMIC 14SF+
Deliverables
Application Note / User Manual
Behavior model, and protected RTL codes
Protected Post layout netlist and Standard
Delay Format (SDF)
Synopsys library (LIB)
Frame view (LEF)
Metal GDS (GDSII)
Test patterns and Test Documentation
Application
PC
Television
Data Storage
Multimedia Devices
Recorders
Mobile Devices
