eDP/DP Tx PHY is designed for chips that perform eDP/DP data communication while operating at low power consumption. The main link is a multi-gigabit transmitter macro which enable speed up to 4.0Gbps data transmitter with optimized power and die size, also it can be easily fabricated and implemented in a video system. The AUX channel is a half-duplex, bidirectional channel consisting of one differential pair, supporting the bit rate of about 1Mbps.
Macro consists of multi-main link transmitter channels, AUX channel, one PLL and bias-gen unit. The main link transmitter performs dedicated P2S, clock generator, driver with pre-emphasis and self-test. Each of the channels can be turned off individually.
Support data rate of main link : 0.6Gbps~4.0Gbps
Utilize per-lane 10/20bit parallel interface for main link
Support Spread Spectrum clock generation: -
One shared PLL for all the lanes
Individual power down for each lane
Support 0~9dB programmable 2-tap FFE (feed forward equalization) for main link