Production Proven, Complex Semiconductor IP Cores

Semiconductor IP Cores

T2M › Risc-V › 100

100

Description

An ultra-low-power, ultra-compact 32-bit microprocessor based on the RISC-V instruction set architecture (ISA). As the smallest processor in our RISC-V CPU family, it is purpose-built for deeply embedded microcontroller applications. With a highly efficient 2-stage pipeline and configurable options, this RISC-V delivers exceptional energy efficiency and area savings while maintaining the flexibility of the open RISC-V ecosystem.

Features

  • RV32 (E/I)(M)(C/Zc)
  • Machine-mode only
  • 2-stage pipeline HW
  • Multiplier and divider individually configurable.
  • Alternative RISC-V C extension or Zc extension.
  • Number of interrupts can be configured to 16 at most
  • Optional Debug support. RISC-V debug architecture, standard 4-wire JTAG debugging interface or cJTAG 2-wire debugging interface
  • One 32-bit AHB-Lite master interface

Applications:

  • Smart Cards & Security Devices
  • Smart Power Grid Controllers
  • Wireless Sensor Networks (WSN)
  • Consumer IoT Devices
  • Industrial Automation Nodes
  • Low-Power Embedded Systems

Delivberales-

Synthesizable RTL with configuration options

  • Documentation & User Guides
    1. Development Support Tools:
    2. FPGA Development Board with user manual
    3. ESWIN Integrated Development Environment (IDE) based on Eclipse CDT
    4. Pre-built toolchain (compiler, assembler, linker, simulator, GDB, libraries)
    5. ESWIN SDK with RTOS support (FreeRTOS, RT-Thread)
  • Debug & Simulation Support (QEMU, OpenOCD, FPGA/HAPS/S2C environments)
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