200- 32 BIT

Description

High-efficiency embedded processor tailored for the IoT and edge device market, combining low-power design, enhanced security, and scalable performance. With support for advanced RISC-V extensions like RV32F, RV32B, and Zicbom, along with optional memory protection and cache management, RISC – V delivers secure, reliable, and high-performance computing for next-generation IoT devices.

Features

• RV32 IMAC(B)(F)_Zicsr_Zifencei_Zicbom
• Machine-Mode, User-Mode
• 2-stage pipeline
• Optional FPU (Floating-Point Unit) supports single precision floating point
• Supports Smepmp. Optional PMP (Physical Memory Protection) unit with configurable regions from 0 to 16
• L1 I$ (L1 Instruction Cache) size is configurable from 4KB to 128KB. Parity/ECC optional
• L1 D$ (L1 Data Cache) size is configurable from 4KB to 128KB. Parity/ECC optional
• Optional TIM (Tightly-Integrated Memory), TIM0 and TIM1, with configurable size from 0KB to 128MB. ECC optional
• Supports CLIC (Core Local Interrupt Controller) with up to 112 fast interrupts Supports NMI (Non-Maskable Interrupt)
• Debug module supports JTAG/cJTAG port Trigger module supports up to 16 hardware breakpoints
• Three 32-bit AHB (Advanced High-performance Bus), one 32-bit AHB slave interface

Applications

• IoT End Devices (sensing, connection & control)
• Smart Home & Building Automation
• Industrial IoT (IIoT) Controllers
• Wearables & Consumer Electronics
• Smart Power & Energy Systems
• Secure Edge Devices with real-time processing needs

Deliverables

• Processor IP Package (synthesizable RTL with configurable options)
• Development Ecosystem:
  1. FPGA Development Board with user guide
  2. ESWIN IDE (Eclipse-based) with toolchain integration
  3. Pre-built Toolchain (compiler, assembler, linker, simulator, GDB, libraries)
  4. SDK with RTOS Support (FreeRTOS & RT-Thread, with interrupt nesting)
• Debug & Simulation Tools (QEMU, OpenOCD, FPGA/HAPS/S2C support)