T2MIP, the global independent semiconductor IP Cores provider & Technology experts, is pleased to announce the immediate availability of its partner’s JEDEC compliant JESD204B Tx and Rx Controller IP Core and JESD204B Tx and Rx SerDes PHY IP Core in 28HPC+ and 40LL nodes which are silicon proven in major Fabs for all High-Density, High-Speed Interface applications.
JESD204B Rx-Tx PHY and Controller IP Core is a mechanism to achieve high-speed inter-device data transfers and deterministic latency across the serial link. JESD204B is a new 12.5 Gbps and 16Gbps serial interface standard for high-speed, high-resolution data converters which provides full support for the JESD204B synchronous serial interface, compatible with JESD204B.01 version specification. Through its compatibility, it provides a simple interface to a wide range of low-cost devices.
The JESD204B Tx and Rx SerDes PHY IP Core in 28HPC+ and 40LL process technologies are embedded with Multiple lanes with data rate from 1Gbps to 16Gbps. A Transceiver version including both receiver and transmitter is also available. With 40bit/32bit/20bit/16bit selectable parallel data bus, Independent per-lane power down control, Programmable transmit amplitude, Programmable 3-tap feed forward equalizer (FFE) and Embedded receiver equalization (CTLE and DFE) to compensate insertion loss, the JESD204B SerDes PHY makes for a very efficient and low power serial interconnect. The Flexible reference clock frequency range and Integrated LC-tank, Ring OSC and Fractional-N PLL allows the support of spread spectrum clock up to 5000ppm, making it a highly adaptable serial interface for superfast data processing.
Compliant with JESD204 specification JESD204A, JESD204B.01, the JESD204B Tx & Rx Controller IP Core supports data rate upto 12.5 Gbps and programmable clock frequency up to 12.5 GHz. With the support of 1 to 8 lanes and converters per receiver and transmitter, the JESD204B Controller is able to support HD-mode. The Controller’s highly structured and layered design allows seamless reporting of various error statistics, allows 10/8b decoding and provides the option of a manual scrambler. The JESD204B is also designed to support different Serdes interfaces and custom bits per lane.
In addition to JESD204B Rx & Tx Controller and PHY IP Cores, T2M ‘s broad silicon Interface IP Core Portfolio includes USB, PCIe, HDMI, Display Port, MIPI, DDR, 10/100/1000 Ethernet, V by One, programmable SerDes, Serial ATA, and many more Controllers with matching PHYs, available in major Fabs in process geometries as small as 7nm. They can also be ported to other foundries and leading-edge processes nodes on request.
These Semiconductor Interface IP Cores are available for immediate licensing either stand alone or with pre-integrated Controllers and PHYs. For more information on licensing options and pricing please drop a request / MailTo
T2MIP is the global independent semiconductor technology experts, supplying complex semiconductor IP Cores, Software, KGD and disruptive technologies enabling accelerated development of your Wearables, IOT, Communications, Storage, Servers, Networking, TV, STB and Satellite SoCs. For more information, please visit: www.t-2-m.com