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EDisplay Port Tx PHY And Controller IP Cores In 12FFC And 40ULP For An Immersive UHD Experience At 8K!!

26 Dec, 2022

T2MIP, the global independent semiconductor IP Cores provider & Technology experts, is pleased to announce the immediate availability of its partner’s VESA standard eDisplay Port / Display Port v1.4 Tx PHY IP Cores in 40nm ULP and 12nm FFC matching Controllers which are silicon proven in major Fabs with minimal power usage and excellent efficiency for a true UHD experience.
Display Port 1.4 Tx PHY and Controller IP cores applies a visually lossless compression system with the help of DSC (Display Stream Compression) and FEC (Forward Error Correction) to achieve an 8K UHD display at 60Hz. With a transmitter PHY supporting 1.62Gbps (RBR) to 8.1Gbps (HBR3) data rates, T2M-IP's DisplayPort version 1.4 compliant Core is a robust, yet energy-efficient, with programmable analogue features, such as inbuilt 100-ohm termination resistors with common-mode biassing and an integrated equalisation with variable strength, make it less energy-intensive.
Higher resolution utilising fewer pins is made possible by the packetized data transfer of the eDisplay Port/Display Port v1.4 Tx in 12FFC and 40ULP process technologies. The DisplayPort 1.4 standard allows for the transmission of Ultra High Definition (UHD) and High Dynamic Range (HDR) video streams through a single DisplayPort interface for high-end display applications with 8K resolution. It also supports HDCP1.4, HDCP2.2, and DSC's bandwidth reduction.
With the extra benefit of backward compatibility, the eDP version 1.4a / DP version 1.4 compliant transmitter enables forward error correction and has customizable (4/2/1) link channels. It also has one AUX channel. Additionally, it supports all advised link rates and bit rates of 1.62/2.7/5.4/8.1Gbps (HBR3). It permits main link operation with 1, 2, or 4 lanes, which may handle the following: SST mode; Normal and Alternate Scrambler Seed Reset; Enhanced and Default Framing Mode. Additionally, our IP Core has Configuration registers that may be programmed using the AMBA interface.
eDisplay Port / Display Port v1.4 Tx Controller and PHY IP cores with a clear lossless video compression technology that multiplies the DisplayPort data transfer capacity and has been used in semiconductor industry’s computing, digital displays, monitors, TVs and other consumer electronics….
In addition to Display Port/eDisplay Port IP Cores, T2M‘s broad silicon Interface IP Core Portfolio includes USB, HDMI, MIPI (CSI, DSI, UniPro, UFS, Soundwire, I3C), PCIe, DDR, 10/100/1000 Ethernet, V by One, programmable SerDes, Serial ATA and many more, available in major Fabs in process geometries as small as 7nm. They can also be ported to other foundries and leading-edge processes nodes on request.
Availability: These Semiconductor Interface IP Cores are available for immediate licensing either stand alone or with pre-integrated Controllers and PHYs. For more information on licensing options and pricing please drop a request / MailTo
About T2M: T2MIP is the global independent semiconductor technology experts, supplying complex semiconductor IP Cores, Software, KGD and disruptive technologies enabling accelerated development of your Wearables, IOT, Communications, Storage, Servers, Networking, TV, STB and Satellite SoCs. For more information, please visit: