T2MIP, the global independent semiconductor IP Cores provider and technology experts, is pleased to announce the immediate availability of its partner’s PCI SIG compliant PCIe 5.0 SerDes PHY IP cores in 12FFC process nodes with matching PCIe 5.0 Controller IP Core, which are silicon proven with high bandwidth and superfast data transfer speed.
The PCIe 5.0 PHY and Controller IP cores support the PCIe 5.0 specification and are compliant with PIPE 5.1. The structured yet simple design allows easy adoption into any design architecture. Lower power consumption is achieved due to support for additional PLL control, reference clock control, and embedded power gating control. The PHY and link layer include backward compatibility support for parallel interfaces: 16 and 32 bit for Gen5 and Gen4, and 10 and 20 bit for Gen3, Gen2, and Gen1. The PCIe SerDes PHY and Digital Controller IP cores provide minimal latency and superfast isochronous data transfer.
The PCIe 5.0 SerDes PHY IP Core in 12nm FFC process technology supports data transfer rates of 2.5 GT per second, 5.0 GT per second, 8.0 GT per second, 16.0 GT per second, and 32 GT per second with four physical lane width. The 12FFC technology includes built in eye monitor and eye checker, dual port PLL with LC tanks, and a three tap FFE for TX preset. Gated power for lowest leakage in L1.2 low power mode, automatic power saving for short reach, and configurable low power mode settings make the PHY suitable for a wide range of power sensitive applications, with operating voltages of 0.8V and 1.2V.
PCIe 5.0 Controller IP Core provides full PCIe controller functionality with Root Complex and Endpoint BFM modes. It supports queuing for eight configurable virtual channels and multi function configurable traffic class to virtual channel queue mapping. Speed and link width negotiation, polarity inversion, lane to lane skew, configurable timers, and timeouts enable high controllability and scaled flow control. An emergency power reduction state enables advanced power management.
These IP core functionalities are verified using NC Verilog simulation software with test benches written in Verilog HDL, which are provided as part of the IP core delivery.
The PCIe 5.0 SerDes PHY IP core and the PCIe 5.0 Controller IP core have been deployed in enterprise computing, storage area networks, wireless and mobile devices, automotive systems, IoT, embedded systems, graphics devices, and other industrial applications.
In addition to PCIe IP cores, T2M’s extensive silicon interface IP portfolio includes USB, HDMI, DisplayPort, MIPI interfaces such as CSI, DSI, UniPro, UFS, SoundWire, and I3C, as well as DDR, 10 100 1000 Ethernet, V by One, programmable SerDes, SD, eMMC, and many more. These IP cores are available across major foundries in process geometries down to 7nm and can be ported to other foundries and advanced process nodes upon request.
Availability: These Semiconductor Interface IP Cores are available for immediate licensing either stand alone or with pre-integrated Controllers and PHYs. For more information on licensing options and pricing please drop a request /
contact@t-2-m.com
About T2M: T2MIP is the global independent
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