TAE320

Description

A 32-bit RISC-V embedded functional safety processor. Based Description ISA RISC-V 32-bit IMAC(B)(F)(P) on the TGE320, the Parity/ECC and Stack Pointer Monitor (SPM) modules are added to compliant with ASIL-B functional safety standards.

Features

• ISA: RISC-V 32-bit IMAC(B)(F)(P)
• Modes: Machine-mode, User-mode
• Security: Supports Smepmp, PMP Region can optional from 0 to 16
• Pipeline: 3-stage pipeline
• TIM: TIM0 and TIM1,with configurable sizes from 0KB to TIM 128MB, ECC optional
• L1 I$: L1 I$ Size configurable from 4KB to 128KB. Parity/ECC optional
• L1 D$: L1 D$ Size configurable from 4KB to 128KB. Parity/ECC optional
• Interrupt: CLIC interrupt controller, supports 496 interrupt requests and non-maskable interrupts (NMI)
• Debug :
  • Debug module: supports JTAG/cJTAG Debug
  • Trace module: supports RISC-V Nexus Trace
• Bus Interface:
  • ICache Port: 32-bit AHB-Lite master interface 
  • Dcache Port: 32-bit AHB-Lite master interface
  • Peripheral Port: 32-bit AHB-Lite master interface
  • Front Port: 32-bit AHB-Lite slave interface
• CoreMark (CoreMarks/MHz): 4.45
• Dhrystone-Legla (DMIPS/MHz): 1.74

Applications

• Industry
• Consumer electronics
• Automotive, etc.

Deliverables

• IP Package 

• Synthesizable RISC-V CPU IP core 

• Simulation Environment with test case demo 

• IP User Manual/ Integration Manual/ Simulation Manual/ Functional Safety Manual (if support) 

• FPGA Development Board Support Package
  • FPGA board
  • User manual
  • Online technical support
  • Offline technical support

• IDE Package
  • IDE (Windows + Linux versions)
  • User guides
  • Pre-built tool suite
  • Pre-built project demos
  • Automated debug and trace process

• Toolchain Package
  • GCC13/GCC14-based toolchain
  • Compiler, assembler, linker
  • QEMU simulator
  • GDB debugger
  • Basic libraries

• SDK
  • MCU SDK  (EMSIS, RTOS support, RTOS interrupt nesting support, etc.) for 32-bit IPs
  • Linux SDK  (Linux OS support) for 64-bit IPs