TGE100

Description

TGE100 is an extremely low power, ultra-compact 32-bit microprocessor based on the RISC-V instruction set architecture (ISA). As the smallest processor in our RISC-V CPU family, it is purpose-built for deeply embedded microcontroller applications. With a highly efficient 2-stage pipeline and configurable options, this RISC-V delivers exceptional energy efficiency and area savings while maintaining the flexibility of the open RISC-V ecosystem.

Features

• ISA: RV32 (E/I)(M)(C/Zc)
• Modes: Machine-mode only
• Pipeline: 2-stage pipeline
• HW Multiplier & Divider: Multiplier and divider individually configurable.
• Code Density: Alternative RISC-V C extension or Zc extension.
• Interrupt: Number of interrupts can be configured to 16 at most
• Debug: Optional Debug support. RISC-V debug architecture, standard 4-wire JTAG debugging interface or cJTAG 2-wire debugging interface
• Bus Inteface: One 32-bit AHB-Lite master interface
• CoreMark (CoreMarks/MHz): 2.11
• Dhrystone-Legla (DMIPS/MHz): 0.79

Applications

• Smart card 
• Smart Power Grid 
• Wireless sensor network  
• Cost-sensitive IoT  
• Microcontrollers

Deliverables

• IP Package 

• Synthesizable RISC-V CPU IP core 

• Simulation Environment with test case demo 

• IP User Manual/ Integration Manual/ Simulation Manual/ Functional Safety Manual (if support) 

• FPGA Development Board Support Package
  • FPGA board
  • User manual
  • Online technical support
  • Offline technical support

• IDE Package
  • IDE (Windows + Linux versions)
  • User guides
  • Pre-built tool suite
  • Pre-built project demos
  • Automated debug and trace process

• Toolchain Package
  • GCC13/GCC14-based toolchain
  • Compiler, assembler, linker
  • QEMU simulator
  • GDB debugger
  • Basic libraries

• SDK
  • MCU SDK  (EMSIS, RTOS support, RTOS interrupt nesting support, etc.) for 32-bit IPs
  • Linux SDK  (Linux OS support) for 64-bit IPs