Description
An ultra-low power, cost-effective 32-bit RISC-V embedded information security processor that implements more than a dozen Anti-tamper security features against a variety of attack models.
Sight: Provides waveform debugging tools, so that users can easily understand the internal state and events of the CPU.

Features
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ISA: RISC-V 32-bit EMC / Zc
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Modes: Machine-mode, User-mode
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Security:
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Supports Smepmp, PMP Region can optional from 0 to 16.
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Supporting more than ten security features such as random polarization of data paths and consistent instruction cycles.
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Pipeline: 2-stage pipeline
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TIM: TIM0 and TIM1, with configurable sizes from 0KB to 128MB, ECC optional
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Interrupt: CLIC interrupt controller, supports 112 interrupt requests and non maskable interrupts (NMI)
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Debug:
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Debug module, supports JTAG / cJTAG
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Trigger module supports up to 16 hardware breakpoints
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Bus Interface:
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Peripheral Port: 32-bit AHB-Lite master interface
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System Port: 32-bit AHB-Lite master interface (Optional)
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Front port: 32-bit AHB-Lite slave interface, used for external access to TIM0 and TIM1
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CoreMark (CoreMarks/MHz): 2.22
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Dhrystone-Legla (DMIPS/MHz): 0.87
Applications
Information security and financial payments.
Deliverables
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Synthesizable RISC-V CPU IP core
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Simulation Environment with test case demo
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IP User Manual/ Integration Manual/ Simulation Manual/ Functional Safety Manual (if support)
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FPGA Development Board Support Package
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FPGA board
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User manual
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Online technical support
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Offline technical support
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IDE Package
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IDE (Windows + Linux versions)
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User guides
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Pre-built tool suite
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Pre-built project demos
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Automated debug and trace process
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Toolchain Package
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GCC13/GCC14-based toolchain
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Compiler, assembler, linker
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QEMU simulator
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GDB debugger
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Basic libraries
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SDK
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MCU SDK (EMSIS, RTOS support, RTOS interrupt nesting support, etc.) for 32-bit IPs
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Linux SDK (Linux OS support) for 64-bit IPs