TAS500

Description

A 64-bit RISC-V application-level functional security processor. Based on TGS500, compliant with ASIL-B functional safety standards.

Features

• ISA: RVA23+Vector Crypto
• Multi-Core: SMP (Symmetric Multiprocessing) supports up to 8 cores in each cluster
• Security: SupportsTEE solution, with up to 64 PMP regions
• Pipeline: 9-stage superscalar in-order pipeline, 2-way decode
• Branch Predictor: L0_BTB, BTB, IJTB, BHT, RAS, Loop Buffer
• L1 I$: Size is configurable from 8KB to 64KB. ECC optional
• L1 D$: Size is configurable from 8KB to 64KB. ECC optional
• Cluster LLC: Size is configurable from 256KB to 4MB, ECC optional
• MMU: SV39, ITLB, DTLB
• Interrupt: CLINT, PLIC
• Debug:
  • Debug module: supports JTAG
  • Trace module: supports RISC-V standard E-Trace/ N-Trace
• Bus Interface: Two 128-bit AXI (Advanced eXtensible Interface) master interfaces, one 128-bit AXI slave interface
• CoreMark (CoreMarks/MHz): 6.27
• Dhrystone-Legla (DMIPS/MHz): 2.90

Applications

• Cloud
• Edge
• Consumer electronics
• Tablets
• Smart TV
• Industrial
• Automotive markets, etc.

Deliverables

• IP Package 

• Synthesizable RISC-V CPU IP core 

• Simulation Environment with test case demo 

• IP User Manual/ Integration Manual/ Simulation Manual/ Functional Safety Manual (if support) 

• FPGA Development Board Support Package
  • FPGA board
  • User manual
  • Online technical support
  • Offline technical support

• IDE Package
  • IDE (Windows + Linux versions)
  • User guides
  • Pre-built tool suite
  • Pre-built project demos
  • Automated debug and trace process

• Toolchain Package
  • GCC13/GCC14-based toolchain
  • Compiler, assembler, linker
  • QEMU simulator
  • GDB debugger
  • Basic libraries

• SDK
  • MCU SDK  (EMSIS, RTOS support, RTOS interrupt nesting support, etc.) for 32-bit IPs
  • Linux SDK  (Linux OS support) for 64-bit IPs