Description
A low-power, high performance iot, microcontroller, etc. that adds L1 cache, B extention, F extention, Zicbomcache operation extention, and Smepmpsecurity extentionfor further enhance performance. Designed for embedded lightweight microcontroller applications.

Features
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ISA: RV32 IMAC(B)(F)_Zicsr_Zifencei_Zicbom
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Modes: Machine-Mode, User-Mode
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Pipeline: 2-stage pipeline
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FPU: Optional FPU Floating-Point Unit) supports single precision floating point
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Security: Supports Smepmp. Optional PMP (Physical Memory Protection) unit with configurable regions from 0 to 16
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L1 I$: L1 I$ (L1 Instruction Cache) size is configurable from 4KB to 128KB. Parity
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L1 D$: L1 D$ (L1 Data Cache) size is configurable from 4KB to 128KB. Parity
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TIM: Optional TIM (Tightly-Integrated Memory), TIM0 and TIM1, with configurable size from 0KB to 128MB
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Interrupt:
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Supports CLIC (Core Local Interrupt Controller) with up to 112 fast interrupts
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Supports NMI (Non-Maskable Interrupt)
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Debug:
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Debug module supports JTAG/cJTAG port
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Trigger module supports up to 16 hardware breakpoint
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Bus Interface: Three 32-bit AHB (Advanced High-performance Bus), one 32-bit AHB slave interface
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CoreMark (CoreMarks/MHz): 4.65
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Dhrystone-Legla (DMIPS/MHz): 1.90
Applications
IoT devices for sensing, connection and control.
Deliverables
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Synthesizable RISC-V CPU IP core
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Simulation Environment with test case demo
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IP User Manual/ Integration Manual/ Simulation Manual/ Functional Safety Manual (if support)
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FPGA Development Board Support Package
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FPGA board
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User manual
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Online technical support
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Offline technical support
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IDE Package
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IDE (Windows + Linux versions)
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User guides
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Pre-built tool suite
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Pre-built project demos
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Automated debug and trace process
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Toolchain Package
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GCC13/GCC14-based toolchain
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Compiler, assembler, linker
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QEMU simulator
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GDB debugger
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Basic libraries
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SDK
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MCU SDK (EMSIS, RTOS support, RTOS interrupt nesting support, etc.) for 32-bit IPs
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Linux SDK (Linux OS support) for 64-bit IPs